Questa & ModelSim
Questa Verification IP
Course Code
285338-US
Software
Questa & ModelSim 2023.3
User Level
Advanced
Pricing ID
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List Price
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Live Online Duration
6 hours for each day for 2 days
This course is for engineers who are verifying designs with standard protocols such as AMBA AXI, PCIe/NVMe, Ethernet, USB, serial, and many more, or designs with DRAM and Flash memories. Questa Verification IP (QVIP) supports these protocols and memories. QVIP comes with a library of protocol-specific sequences and test plans. QVIP can drive the bus and check responses with scoreboards and SystemVerilog Assertions. After completion of this course, engineers will be able to generate a UVM testbench with QVIP Configurator and integrate QVIP into existing UVM test benches.
Hands-on lab exercises reinforce lecture and discussion topics under the guidance of our industry expert instructors.
PREREQUISITES
Prerequisites
- Familiarity with concepts of hardware verification
- Knowledge of the SystemVerilog language, especially Object-Oriented Programming and randomization
- Basic knowledge of UVM, equivalent to having attended the Mentor SystemVerilog UVM course
PROVIDED COURSE MATERIALS
Class Package
PRIMARY COURSE TOPICS
What You’ll Learn
- Overview of Questa Verification IP (QVIP)
- How to run QVIP Configurator in order to build a UVM testbench
- Configurator inputs including how to connect and configure
- Configurator outputs including the UVM testbench, netlists, and simulation support files
- The structure of QVIP including the interface, bus functional model, assertions, connectivity module, and UVM testbench
- How to control QVIP with the configuration classes and structures
- The QVIP scoreboard and its memory
- The slave memory model
- How to learn more about QVIP through the documentation
- Examples included with QVIP
- Basics of AMBA AXI4