On-Demand Training - Functional Verification
Description
This library contains learning paths that help you master functional verification tools, and the development of test environments using HDL-based methodologies. Learn how to use ModelSim/Questa GUI and command line to verify and debug HDL designs in interactive mode or build batch mode scripts for fast simulations.
- 12 month subscription
- Access to cloud-based environment for hands-on lab exercises
- Access to new training content added during the subscription period
- Knowledge assessments to measure learning progress
Explore This On-Demand Training
Chapters
learning path
- Questa HDL Simulation Learning Path Overview
- Questa Introduction to Simulation
- Questa Basic Simulation Using Commands
- Visualizer Graphical User Interface
- Questa Working with Projects
- Questa Mixed-HDL Designs
- Questa Core HDL Simulation Exam
Questa Core HDL Simulation
Learn how to use Questa GUI and command line to verify and debug HDL designs in interactive mode or build batch mode scripts for fast simulations.
Questa: Simulation in the Digital Design Flow
Questa Core HDL Simulation 7 Chapters
Learn how to use Questa GUI and command line to verify and debug HDL designs in interactive mode or build batch mode scripts for fast simulations.
1 Questa HDL Simulation Learning Path Overview 1 Topic
- Learning Path Overview
2 Questa Introduction to Simulation 11 Topics
- Questa: Simulation in the Digital Design Flow
- Questa: Simulation Process
- Knowledge Check 1: Questa Introduction to Simulation
- Questa: Overview of Features and Supported Industry Standards
- Questa: Modes of Operation
- Visualizer: Typical Usage Flows
- Knowledge Check 2: Questa Introduction to Simulation
- Questa/Visualizer: Getting help
- Knowledge Check 3: Questa Introduction to Simulation
- Lab 1: Questa Documentation and Help
- Assessment: Questa Introduction to Simulation
3 Questa Basic Simulation Using Commands 12 Topics
- Questa: Command Line Overview
- Questa: Libraries and Design Units
- Knowledge Check 1: Questa Basic Simulation Using Commands
- Questa: Compilation and Optimization commands
- Questa: Optimization with QIS Flow
- Questa: QIS Flow Examples
- Questa: Basic Simulation Commands
- Knowledge Check 2: Questa Basic Simulation Using Commands
- Questa: Simple Stimulus Using Simulator
- Knowledge Check 3: Questa Basic Simulation Using Commands
- Lab 2: Questa Command Line Simulation
- Assessment: Questa Basic Simulation Using Commands
4 Visualizer Graphical User Interface 18 Topics
- Visualizer: Overview of GUI Operation
- Visualizer: Design Window
- Visualizer: Design Exploration with the Advanced Search
- Knowledge Check 1: Visualizer GUI
- Visualizer: Source Code Debug
- Visualizer: Variables Window
- Visualizer: Adding Signals to the Wave Window
- Knowledge Check 2: Visualizer GUI
- Visualizer: Wave Window - Part 1
- Visualizer: Wave Window - Part 2
- Visualizer: Tracing Drivers and Receivers
- Visualizer: X Tracing
- Knowledge Check 3: Visualizer GUI
- Visualizer: Memory Window
- Visualizer: FSM Window
- Knowledge Check 4: Visualizer GUI
- Lab 3: Introduction to the Visualizer GUI
- Assessment: Visualizer Graphical User Interface
5 Questa Working with Projects 9 Topics
- Questa: What is a Project?
- Questa: Creating a project in the GUI
- Questa: Setting project properties
- Knowledge Check 1: Questa Working with Projects
- Questa: Using a Project in the GUI
- Questa: Using The project Command
- Knowledge Check 2: Questa Working with Projects
- Lab 4: Questa Working with projects
- Assessment: Questa Working with projects
6 Questa Mixed-HDL Designs 8 Topics
- Questa: Mixed-HDL Design Considerations
- Questa: Verilog inside VHDL
- Questa: VHDL inside Verilog
- Knowledge Check 1: Questa Mixed-HDL Designs
- Questa: Accessing objects in a mixed Design
- Knowledge Check 2: Questa Mixed-HDL Designs
- Lab 5: Questa Mixed HDL Design
- Assessment: Questa Mixed-HDL Designs
7 Questa Core HDL Simulation Exam 1 Topic
- Level 1 Exam - Questa Core: HDL Simulation
Chapters
learning path
- ModelSim/Questa Tcl/TK Overview
- ModelSim/Questa Code Coverage
- ModelSim/Questa Language Support and Gate Level Simulations
- ModelSim/Questa Finite State Machine Viewer
- ModelSim/Questa Selected Debugging Topics
- ModelSim/Questa Core: Advanced Topics Exam
ModelSim / Questa Core Advanced Topics
This learning path enables you to extend your knowledge of ModleSim/QuestaSim functionality and to efficiently analyze and debug HDL code.
ModelSim / Questa: Why Use Tcl/Tk?
ModelSim / Questa Core Advanced Topics 6 Chapters
This learning path enables you to extend your knowledge of ModleSim/QuestaSim functionality and to efficiently analyze and debug HDL code.
1 ModelSim/Questa Tcl/TK Overview 10 Topics
- ModelSim / Questa: Why Use Tcl/Tk?
- ModelSim / Questa: Tcl Overview
- ModelSim / Questa: Tcl Syntax
- ModelSim / Questa: Using vsim Commands in Tcl Scripts
- ModelSim / Questa: Simple Simulation Scripts
- Knowledge Check 1: ModelSim/Questa - Tcl/Tk Overview
- ModelSim / Questa: Tk Widgets and Custom GUI Buttons
- Knowledge Check 2: ModelSim/Questa - Tcl/Tk Overview
- Lab: ModelSim/Questa - Using Scripts and Tk Widgets in Simulation
- Assessment: ModelSim/Questa - TCL/TK Overview
2 ModelSim/Questa Code Coverage 15 Topics
- ModelSim / Questa: Purpose and Benefits of Code Coverage
- ModelSim / Questa: Types of Code Coverage
- Knowledge Check 1: ModelSim/Questa - Code Coverage
- ModelSim / Questa: Invoking Code Coverage
- ModelSim / Questa: Code Coverage Analysis Windows
- Knowledge Check 2: ModelSim/Questa - Code Coverage
- ModelSim / Questa: Managing Coverage Exclusions
- ModelSim / Questasim: Reporting Coverage
- Knowledge Check 3: ModelSim/Questa - Code Coverage
- Lab: ModelSim/Questa - Performing Code Coverage
- Modelsim / QuestaSim: Saving Coverage Data (UCDB)
- ModelSim / Questa: Managing Coverage Data
- Knowledge Check 4: ModelSim/Questa Code Coverage
- Lab: ModelSim/Questa - Analyzing Code Coverage Results
- Assessment: ModelSim/Questa - Code Coverage
3 ModelSim/Questa Language Support and Gate Level Simulations 13 Topics
- ModelSim / Questa: SDF Annotation, VHDL and VHDL VITAL
- ModelSim / Questa: VHDL Coding for Performance
- Knowledge Check 1: ModelSim/Questa - Language Support
- ModelSim / Questa: Verilog / SystemVerilog Version Support
- ModelSim / Questa: How to Compile SV Files
- ModelSim / Questa: Verilog Coding for Maximum Performance
- Knowledge Check 2: ModelSim/Questa - Language Support
- ModelSim / Questa: Verilog Delay Modes for Gate Level Simulations
- ModelSim / Questa: Verilog SDF Timing Annotation
- ModelSim / Questa: Verilog Gate Level Optimizations
- Knowledge Check 3: ModelSim/Questa - Language Support
- Lab: ModelSim/Questa - Gate Level Simulation
- Assessment: ModelSim/Questa - Gate Level
4 ModelSim/Questa Finite State Machine Viewer 6 Topics
- ModelSim/Questa: FSM Recognition
- Knowledge Check 1: ModelSim/Questa FSM
- ModelSim/Questa: Viewing FSM in GUI
- Knowledge Check 2: ModelSim/Questa FSM
- Lab: ModelSim/Questa Finite State Machine
- Assessment: ModelSim/Questa FSM
5 ModelSim/Questa Selected Debugging Topics 18 Topics
- ModelSim / Questa: Why Debug is Needed?
- ModelSim / Questa: Checkpoint and Restore
- ModelSim / Questa: Contention and Float Checking
- ModelSim / Questa: Toggle and Stability Checking
- ModelSim / Questa: Iteration Violations
- Knowledge Check 1: ModelSim/Questa - Debugging
- ModelSim / Questa: Post Simulation Analysis
- ModelSim / Questa: IP Integrity
- Lab: ModelSim / Quest - Iteration Limit
- ModelSim / Questa: Hyperlinked Navigation
- ModelSim / Questa: Tracing Readers and Drivers
- Knowledge Check 2: ModelSim/Questa Debugging
- ModelSim / Questa: Waveform Grouping
- ModelSim / Questa: Saving Waveforms Between Cursors
- ModelSim / Questa: Waveform Expanded Time
- Knowledge Check 3: ModelSim/Questa - Debugging
- Lab: ModelSim/Questa - Logic Error
- Assessment: ModelSim/Questa - Debugging Topics
6 ModelSim/Questa Core: Advanced Topics Exam 1 Topic
- Level 1 Certification - ModelSim/Questa Core: Advanced Topics
Chapters
learning path
- Mastering Questa Learning Path Overview
- Verification Plan
- Code Coverage
- Functional Coverage
- Test Tracking
- SV Class Debugging
- Performance
- Debugging SystemVerilog Assertions
- Constrained Random Verification
- Performance Profiling
- Transactions
- Using DPI
- Mastering Questa Exam
Mastering Questa
This learning path helps you master Questa’s advanced functional verification environment in order to manage your tests and debug verification bugs.
Questa: Purpose and Benefits of Code Coverage
Mastering Questa 13 Chapters
This learning path helps you master Questa’s advanced functional verification environment in order to manage your tests and debug verification bugs.
1 Mastering Questa Learning Path Overview 1 Topic
- Learning Path Overview
2 Verification Plan 15 Topics
- Questa: Verification Motivations and Process
- Questa: Verification Plan Components
- Knowledge Check 1: Verification Plan
- Questa: Verification Management Tasks
- Questa: Unified Coverage Database (UCDB)
- Knowledge Check 2: Verification Plan
- Questa: Verification Management Flow
- Questa: Creating a Verification Plan
- Questa: Verification Plan Contents
- Knowledge Check 3: Verification Plan
- Questa: Export and Import a Verification Plan
- Questa: Merging Verification Plan with Test Data
- Knowledge Check 4: Verification Plan
- Lab: The Verification Plan
- Assessment: Verification Plan
3 Code Coverage 15 Topics
- Questa: Purpose and Benefits of Code Coverage
- Questa: Types of Code Coverage
- Knowledge Check 1: Code Coverage
- Questa: Invoking Code Coverage
- Questa: Code Coverage Analysis Windows
- Knowledge Check 2: Code Coverage
- Questa: Managing Coverage Exclusions
- Questa: Reporting Coverage
- Knowledge Check 3: Code Coverage
- Lab: Performing Code Coverage
- Questa: Saving Coverage Data (UCDB)
- Questa: Managing Coverage Data
- Knowledge Check 4: Code Coverage
- Lab: Analyzing Code Coverage Results
- Assessment: Code Coverage
4 Functional Coverage 9 Topics
- Questa: What is Functional Coverage?
- Questa: How to Implement Functional Coverage?
- Knowledge Check 1: Functional Coverage
- Questa: Functional Coverage Plan
- Questa: Filtering and Sampling Coverage
- Questa: Functional Coverage in the GUI
- Knowledge Check 2: Functional Verification
- Lab: Functional Coverage
- Assessment: Functional Coverage
5 Test Tracking 11 Topics
- Questa: Creating a Test Environment
- Questa: Storing Attributes in the UCDB
- Questa: Coverage View Mode
- Knowledge Check 1: Test Tracking
- Questa: Post-Simulation Analysis
- Questa: Optimizing Regression Runs
- Questa: Verification Analysis
- Questa: Generating HTML Coverage Reports
- Knowledge Check 2: Test Tracking
- Lab: Test Tracking
- Assessment: Test Tracking
6 SV Class Debugging 23 Topics
- Questa: Enabling Debugging for SV Classes
- Questa: Questa Class Nomenclature
- Questa: describe and examine Commands
- Questa: Class Tree, Graph and Instances Windows
- Knowledge Check 1: SV Class Debugging
- Questa: Watch, Locals and Call Stack Windows
- Questa: Viewing Class instances in the Wave Window
- Questa: Finding Information about Your Classes
- Knowledge Check 2: SV Class Debugging
- Questa: User-Defined Radices
- Questa: Memory Windows
- Questa: Processes and Locals Windows
- Knowledge Check 3: SV Class Debugging
- Questa: Waveform Expanded Time
- Questa: Tracing Readers and Drivers
- Questa: Message Viewer window
- Questa: Debugging Macros and the Call Command
- Knowledge Check 4: SV Class Debugging
- Questa: UVM-Aware Debug
- Questa: Transaction Streams
- Knowledge Check 5: SV Class Debugging
- Lab: SystemVerilog Debugging
- Assessment: SV Class Debugging
7 Performance 12 Topics
- Questa: What is vopt?
- Questa: Optimization Flows
- Questa: Preserving Visibility
- Questa: Optimization of Parameters and Generics
- Questa: Preserving VPI/PLI Visibility
- Knowledge Check 1: Performance
- Questa: Gate Level Optimization
- Questa: vopt with Compiled SDF
- Questa: The PDU Flow
- Knowledge Check 2: Performance
- Lab: Performance
- Assessment: Performance
8 Debugging SystemVerilog Assertions 11 Topics
- Questa: Assertion-Based Verification
- Questa: Assertions Window
- Questa: Configure Assertions
- Knowledge Check 1: Debugging SystemVerilog Assertions
- Lab: Assertions Window
- Questa: Assertions in the Wave Window
- Questa: Assertion Thread Viewer Window
- Questa: Usage of SV Bind Construct with Assertions
- Knowledge Check 2: Debugging SystemVerilog Assertions
- Lab: Debugging SystemVerilog Assertions
- Assessment: Debugging SystemVerilog Assertions
9 Constrained Random Verification 7 Topics
- Questa: Randomization
- Questa: Constraint Random Coding Guidelines
- Questa: Constraint Solvers
- Questa: Debugging Randomization Failures
- Knowledge Check 1: Constrained Random Verification
- Lab: Debugging a Failure in the Constraint Solver
- Assessment: Constrained Random Verification
10 Performance Profiling 7 Topics
- Questa: Performance Profiling
- Questa: Viewing Profiler Results
- Knowledge Check 1: Performance Profiling
- Questa: Memory Allocation Profiler
- Questa: Capacity Analysis
- Knowledge Check 2: Performance Profiling
- Assessment: Performance Profiling
11 Transactions 6 Topics
- Questa: What is a Transaction?
- Questa: Transaction Recording Flow
- Questa: Viewing Related Transactions in the Wave Window
- Knowledge Check 1: Transactions
- Lab: Transaction Recording and Viewing
- Assessment: Transactions
12 Using DPI 9 Topics
- Direct Programming Interface Introduction
- Direct Programming Interface Importing C Routines
- Direct Programming Interface Debugging with Questa
- Lab: Introduction to DPI-C
- Direct Programming Interface Models With Storage
- Direct Programming Interface C Calling SystemVerilog
- Knowledge Check: Using DPI
- Lab: C Testbench
- Assessment: Using DPI
13 Mastering Questa Exam 1 Topic
- Level 1 Certification - Mastering Questa
Chapters
learning path
- Introduction to SystemC
- SystemC in Questa SIM
Questa SIM SystemC
In this learning path you will receive an overview of SystemC and learn how to simulate SystemC designs in Questa.
Questa SIM SystemC: Introduction to C++
Questa SIM SystemC 2 Chapters
In this learning path you will receive an overview of SystemC and learn how to simulate SystemC designs in Questa.
1 Introduction to SystemC 10 Topics
- Questa SIM SystemC: Introduction to C++
- Questa SIM SystemC: Introduction to SystemC
- Questa SIM SystemC: SystemC Basic Contructs
- Knowledge Check 1: Introduction to SystemC
- Questa SIM SystemC: SystemC Design Hierarchy
- Questa SIM SystemC: SystemC Data Types
- Questa SIM SystemC: SystemC Time
- Knowledge Check 2: Introduction to SystemC
- Lab 1: SystemC Hello World
- Assessment: Introduction to SystemC
2 SystemC in Questa SIM 6 Topics
- Questa SIM SystemC: Questa SIM SystemC General Flow
- Questa SIM SystemC: Mixed HDL Support
- Questa SIM SystemC: SystemC Different Flows
- Lab 2: SystemC Shared Library Flow
- Lab 3: SystemC Archived Models
- Assessment: SystemC in Questa SIM
Chapters
learning path
- Code Coverage
- Profiler
- Controlling X-Propagation using xprop
- Race Detection
Questa Core/Visualizer Advanced Topics
This learning path enables you to extend your knowledge of QuestaSim functionality and debug HDL design using the Visualizer Debug Environment.
Questa Core/Visualizer Advanced Topics 4 Chapters
This learning path enables you to extend your knowledge of QuestaSim functionality and debug HDL design using the Visualizer Debug Environment.
1 Code Coverage 17 Topics
- Purpose and Benefits of Code Coverage
- Types of Code Coverage
- Enabling & Invoking Code Coverage
- Knowledge Check 1: Questa Code Coverage
- Coverage Windows in Visualizer Part 1
- Coverage Windows in Visualizer Part 2
- Testplan Analysis
- Knowledge Check 2: Questa Code Coverage
- Coverage Exclusion
- Coverage Reports
- Knowledge Check 3: Questa Code Coverage
- Lab 1: Performing Code Coverage and Generating Coverage Reports
- Managing Coverage
- Merging Coverage Strategies
- Knowledge Check 4: Questa Code Coverage
- Lab 2: Merging UCDB
- Assessment: Code Coverage
2 Profiler 18 Topics
- Purpose of Using the Profiler
- Profiler Flow
- Profiler Engines - Usage Profiler
- Knowledge Check 1: Profiler
- Profiler Engines - Invoking Performance Profiler
- Viewing Performance Profiler Results Part 1
- Viewing Performance Profiler Results Part 2
- Knowledge Check 2: Profiler
- Profiler Engines - Solver Profiler
- Knowledge Check 3: Profiler
- Profiler Engines - Invoking Memory Profiler
- Viewing Memory Profiler Results
- Knowledge Check 4: Profiler
- Compare Profiler Results
- Profiler Reporting
- Knowledge Check 5: Profiler
- Lab 3: Analyzing Performance Using Visualizer Profiler
- Assessment: Profiler
3 Controlling X-Propagation using xprop 6 Topics
- xprop: Simulation with Xs
- xprop Modes
- xprop Usage
- xprop Use Model
- Lab 4: Controlling X-Propagation Using xprop
- Assessment: Controlling X-Propagation Using xprop
4 Race Detection 5 Topics
- Race Condition Overview
- Race Detection Part 1
- Race Detection Part 2
- Lab 5: Detecting and Managing Simulation Races
- Assessment: Race Detection
On-Demand Training - Functional Verification
Receive unlimited access to all new content added during your active subscription.
During your subscription period, you will automatically receive access to all new content added to the library, including training on new product releases and technology updates to maximize your proficiency.
On-Demand Training - Functional Verification
- 12 month subscription
- Access to cloud-based environment for hands-on lab exercises
- Access to new training content added during the subscription period
- Knowledge assessments to measure learning progress
Starting at
USD $2500.00 / year
USD $2500.00 / year