HyperLynx
HyperLynx Serial Channel Design
Course Code
285340-BR
Software
HyperLynx vx2.8
Language
Português
User Level
All
List Price
Contact Us
Price may not include taxes applicable to your billing region
LIVE Online Duration
6 hours for each day for 3 days
The HyperLynx Serial Channel Design course will help you effectively and efficiently use HyperLynx in designing your serial channels. The class guides the student through the usage of the HyperLynx SerDes Wizards to both develop constraints for layout, set up, and run the SerDes Wizards to verify compliance to SerDes protocols without the need for silicon models and evaluate the channels when IBIS-AMI compliant models are available.
PREREQUISITES
Prerequisites
- Familiarity with concepts of designing serialized/deserialized (SerDes) channels
- HyperLynx Signal Integrity Analysis
- Students are expected to complete the pre-requisite ODT chapter on serial channel design theory prior to attending this class
PROVIDED COURSE MATERIALS
Class Package
PRIMARY COURSE TOPICS
What You’ll Learn
- How to use HyperLynx to develop constraints for a SerDes channel
- How to use HyperLynx to verify the compliance of a SerDes channel to a protocol
- How to use HyperLynx to evaluate the interaction of a channel and vendor-provided IBIS-AMI compliant models
- How to process design data from the Xpedition integrated flow to HyperLynx BoardSim
Throughout this course, extensive hands-on lab exercises provide you with practical experience using HyperLynx software. Hands-on lab topics include:
- Using the SerDes Compliance Check Wizard in LineSim
- Xpedition Integrated tool flow
- Overview opt the post-layout analysis methodology of a multi-board system
- A review of LineSim schematic basics as applied to a SerDes channel
- Working with IBIS-AM I models
- Using the SerDes Wizards to sweep channel parameters
- How to incorporate 3D models generated by the Full-Wave Solver using the via symbol in LineSim
- Using HyperLynx 3D Explorer and Full-wave Solver to create 3D models for different locations of stitching vias by sweeping their locations
- How to sweep the 3D models created by the 3D Explorer/Full-wave Solver process in the LineSim
- Exporting data from Xpedition Layout and suggested location for analyses
- Review of multi-board projects in BoardSim and analysis settings
- Running the SerDes Compliance Check Wizard on multi-board Ethernet channels in BoardSim
- Running the SerDes IBIS-AMI/S-Parameter Batch Wizard on multi-board PCIe channels in BoardSim