Calibre
Calibre: Using DRC/LVS Rules
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Course Overview
The Calibre product suite is the industry standard for deep sub-micron physical verification. Learn how to leverage the full power of Calibre nmDRC and Calibre nmLVS by attending the “Calibre Fundamentals: Performing DRC/LVS” course. This course will teach you to effectively use Calibre nmDRC and Calibre nmLVS software in your layout verification flow and will empower you to analyze DRC and LVS results successfully in coordination with a layout editor. The lecture modules will guide you through the various concepts underlying state-of-the-art layout verification techniques and specific aspects of the Calibre nmDRC and Calibre nmLVS toolsets.
Hands-on lab exercises will reinforce lecture topics and provide you with extensive tool usage experience under the guidance of our industry expert instructors. This course employs the powerful Calibre DESIGNrev layout viewer in all labs.
Prerequisites
- Knowledge of IC layout techniques and procedures
- Experience with an IC layout editing tool
- Familiarity with UNIX/Linux
- Knowledge of layout verification concepts and tools (helpful but not required)
PRIMARY COURSE TOPICS
You Will Learn How To
- Use Calibre nmDRC and Calibre nmLVS proficiently in the flat and hierarchical modes
- Debug flat and hierarchical DRC and LVS results using Calibre RVETM (Results Viewing Environment) and a layout editor
- Interpret the various specification statements in your rule file dealing with input files, results databases and reports, along with other useful rule file statements
- Interpret simple and complex DRC checks such as measurement and ERC checks
- Identify and locate many LVS-related problems such as shorts and opens, floating or isolated nets, pin swapping, device problems, soft connections, and texting (naming) problems
- Use the powerful Calibre Interactive Graphical User Interface