HDL & Other Languages
HDL Designer Series

Course Code
HDL & Other Languages 2018.1
User Level
Pricing ID
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Live In-Person Duration
2 days

This class teaches you to use HDL Designer Series effectively in your FPGA or ASIC design process. The lecture takes you through the HDL Designer Series design flow. This includes modeling the design with both graphics and text, generating HDL, and then simulating and animating the design to verify behavior.


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You will learn how to

  • Set up libraries to hold your designs
  • Model hierarchy and connectivity using block diagrams and IBD
  • Model finite state machines with state diagrams
  • Model sequential processes with flow charts
  • Model combinatorial circuits with truth tables
  • Create and edit component symbols
  • Generate HDL for your graphical/textual design
  • Compile your design for simulation
  • Simulate your design using ModelSim®
  • Animate and debug your design
  • Reuse components
  • Convert existing HDL designs into graphical/textual HDL Designer Series designs
  • Create test benches
  • Manage your design using version management
  • Ensure your design meets required design rules using DesignChecker
  • Interface with a wide range of downstream tools (compilers, simulators, and synthesis tools)
  • Trace requirement references between ReqTracerTM and HDL Designer