Questa & ModelSim
ModelSim / Questa Core: Advanced Topics

Course Code
Questa & ModelSim 2021.1
User Level
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Training Center Duration
2 days

ModelSim/Questa Core: Advanced Topics teaches you to capitalize on the extensive capabilities of ModelSim/Questa Core to effectively and efficiently analyze and debug digital HDL designs. Using various ModelSim / Questa Core features and techniques, you will learn how to produce higher performance test benches, more reliable device-under-test models, and greater confidence in simulation thoroughness and completeness.



  • The student should have VHDL or Verilog knowledge prior to attending this course
  • The student should have beginner ModelSim / Questa Core skills prior to attending this course, or take the ModelSim / Questa Core: HDL Simulation training class.

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What You Will Learn

  • Use advanced debugging concepts and methods.
  • Address advanced design topics and issues
  • Take advantage of advanced cross-window capabilities supporting debugging
  • Manipulate designs and the ModelSim environment using Tcl/Tk
  • Customize design monitors and comparators using Tcl/Tk
  • Determine design “Code Coverage” for verification scenarios
  • Use ModelSim in debugging and performance modes
  • Use the profiler to find bottlenecks in your code
  • Use “Virtual Objects” to explore designs under test
  • Perform advanced design probing with “Signal Spy”
  • Create and compare multiple datasets
  • Use advanced waveform comparison features
  • Visualize and debug Finite State Machines with the FSM Viewer
  • Use ModelSim for simulating VHDL, Verilog, and SystemVerilog designs
  • Analyze and improve design and end product performance from high-level abstract design description through gate-level implementations
  • Tracing the cause of any signal event or all possible drivers of a signal
  • Debug multiple types of specific design errors