This course introduces Embedded Deterministic Test (EDT™) technology and Tessent TestKompress to engineers already familiar with Design-for-Test, but find that existing tools do not adequately deal with today’s aggressive design nodes. It is specially targeted towards those engineers working with ASIC/IC/SOC design projects where pattern size and test times are issues.

Hands-on labs are designed to reinforce key concepts through practical experience and to develop proficiency with the Mentor Graphics Tessent tool suite under the guidance of our industry-expert instructors.