Course Overview

Layout Versus Schematic (LVS) verification has always played a critical role in the IC design process. Calibre nmLVS continues to be the pre-eminent tool for this task. Enhancements continue to be introduced on an ongoing basis that extends Calibre’s capabilities and further streamlines the LVS debugging task. This course will bring you up to date with all of these new features and help sharpen your LVS debugging skills through a series of LVS case studies. Each case represents a unique LVS problem and includes a step-by-step solution. Solutions will be demonstrated in real-time through actual tool execution, allowing students to experience each step and to interact with the instructor to explore alternatives.

Hands-on lab exercises will reinforce lecture and discussion topics under the guidance of our industry expert instructors. Each exercise will provide the opportunity to apply problem-solving skills and utilize tool features presented in the case studies.