Questa Core: HDL Simulation teaches users who are new to using Questa SIM for HDL simulation how to effectively use Questa Core to verify VHDL, Verilog, SystemVerilog, and mixed HDL designs. You will learn how Questa Core supports HDL behavioral simulations, and some basic concepts in the digital design flow. Also, you will receive an introduction on how to invoke the Visualizer debug environment to debug the simulation results from Questa.
Throughout this course, extensive hands-on lab exercises provide you with practical experience in using Questa Core and Visualizer Debug Environment. Hands-on lab topics include: