Questa & ModelSim
ModelSim / Questa Core: HDL Simulation

Course Code
239711-US
Software
Questa & ModelSim 2022.2
Language
English
User Level
All
List Price
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LIVE Online Duration
2 days

ModelSim / Questa Core: HDL Simulation teaches users new to using ModelSim or Questa SIM for HDL simulation how to effectively use ModelSim / Questa Core to verify VHDL, Verilog, SystemVerilog, and mixed HDL designs. You will learn how ModelSim / Questa Core supports HDL behavioral simulations, and some basic concepts in the digital design flow. Also, you will receive an introduction on how to invoke the Visualizer debug environment to debug the simulation results from Questa. Hands-on lab exercises will reinforce lecture and discussion topics and provide you with extensive tool usage experience under the guidance of our industry expert instructors.

PREREQUISITES

Prerequisites

  • Some VHDL or Verilog knowledge
  • Some familiarity with digital design concepts

PROVIDED COURSE MATERIALS
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PRIMARY COURSE TOPICS

You Will Learn How To

  • Invoke the ModelSim / Questa Core program
  • Prepare VHDL and Verilog data for use by ModelSim / Questa Core
  • Create and use design libraries
  • Use ModelSim / Questa Core commands to run a simulation
  • Invoke Visualizer Debug Environment
  • Create a simple simulation script
  • Use ModelSim / Questa Core for batch simulations
  • Use the ModelSim / Questa Core Graphical User Interface
  • Create a ModelSim / Questa Core project
  • Simulate VHDL or Verilog designs
  • Simulate mixed VHDL/Verilog designs