Questa & ModelSim
Questa Core HDL Simulation

Course Code
Questa & ModelSim 2023.2
User Level
Pricing ID
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Live Online Duration
2 days

Questa Core: HDL Simulation teaches users who are new to using Questa SIM for HDL simulation how to effectively use Questa Core to verify VHDL, Verilog, SystemVerilog, and mixed HDL designs. You will learn how Questa Core supports HDL behavioral simulations, and some basic concepts in the digital design flow. Also, you will receive an introduction on how to invoke the Visualizer debug environment to debug the simulation results from Questa.


  • Some VHDL or Verilog knowledge
  • Some familiarity with digital design concepts

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Learning Services, EDA Germany


What You’ll Learn

  • Invoke the Questa Core program
  • Prepare VHDL and Verilog data for use by Questa Core
  • Create and use design libraries
  • Use Questa Core commands to run a simulation
  • Invoke Visualizer Debug Environment
  • Use Questa Core for batch simulations
  • Use the Visualizer Graphical User Interface
  • Create a Questa Core project
  • Simulate VHDL or Verilog designs
  • Simulate mixed VHDL/Verilog designs

Throughout this course, extensive hands-on lab exercises provide you with practical experience in using Questa Core and Visualizer Debug Environment. Hands-on lab topics include:

  • Invoke and use basic simulation commands
  • Create design file and Waveform database file for Visualizer
  • Invoke Visualizer Debug Environment
  • Debug simulation results from Questa Core using Visualizer
  • Create data libraries and simulate VHDL and Verilog designs
  • Detect Verilog hazards
  • Create a VHDL project
  • Detect and fix an error in a VHDL design
  • Create and simulate a mixed VHDL/Verilog design