Visualizer
Questa Core/Visualizer Advanced Topics
Course Code
239712-US
Software
Visualizer 2021.1
User Level
All
Pricing ID
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List Price
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Live Online Duration
6 hours for each day for 3 days
Questa® Core/Visualizer: Advanced Topics teaches you to capitalize on the extensive capabilities of Questa Core to effectively and efficiently simulate digital HDL designs. Also, analyze and debug the simulation results using Visualizer Debug Environment. Using various Questa Core/Visualizer features and techniques, you will learn how to produce higher-performance test benches, more reliable device-under-test models, and greater confidence in simulation thoroughness and completeness.
PREREQUISITES
Prerequisites
- The student should have VHDL or Verilog knowledge prior to attending this course
- The student should have beginner Questa Core/Visualizer skills prior to attending this course, or take the Questa Core: HDL Simulation training class.
PROVIDED COURSE MATERIALS
Class Package
PRIMARY COURSE TOPICS
What You Will Learn
- Use advanced debugging concepts and methods.
- Take advantage of Visualizer capabilities supporting debugging
- Determine design “Code Coverage” for verification scenarios
- Generate Code Coverage Reports
- Merge code coverage data from multiple simulations (regular, coverstore, adaptive, block to top, and parallel merge)
- Running simulation in Post and Live Simulation modes
- Working with Elab, PDU, and Checkpoint Restore
- Use the Visualizer profiler to find bottlenecks in your code
- Use xprop to control x-propagation
- Detect simulation races
- Use Questa for simulating VHDL, Verilog, and SystemVerilog designs
- Analyze and improve design and end-product performance from high-level abstract design description through gate-level implementations