Calibre Fundamentals: Working With PERC

Course Code
Calibre 2021.2
User Level
List Price
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Training Center Duration
1 day

Course Overview

Reliability is a growing concern for integrated circuit designers. In response to this growing need, Mentor Graphics has developed Calibre PERC to address reliability challenges that arise during the circuit and electrical verification process. PERC is specifically designed to perform electrostatic discharge (ESD) and multiple power domain checks. Calibre PERC allows you to customize ERC checks at the schematic level as well as geometrical and electrical checks at layout, which gives you more power and flexibility to handle emerging circuit verification demands for design implementation.

This course will help you understand the wide breadth of problem areas addressed by Calibre PERC, including ESD, advanced ERC, multiple power domains, layout point-to-point resistance, and layout current density. The course will introduce you to the use of this powerful tool and will provide a basic understanding of setting up and running Calibre PERC jobs. Calibre PERC concepts will be demonstrated through a collection of detailed case studies. Students will be able to explore Calibre PERC job options and debugging techniques through the use of hands-on lab exercises. The course includes a Calibre overview module for those students not familiar with Calibre applications.



  • Familiarity with basic electronic circuit design techniques
  • Some knowledge of the Spice netlist format
  • Experience with typical circuit Electrical Rule Checks (ERC) and/or Electrostatic
  • Discharge (ESD) protection is helpful but not required
  • Experience using Unix or Linux is helpful but not required

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You Will Learn How To

  • Create job-specific Calibre PERC control files.
  • Invoke Calibre PERC from the command line and from the interactive GUI.
  • Open Calibre PERC results in Calibre RVE.
  • Use Calibre RVE to highlight PERC results in netlist, schematic, and layout views.
  • Apply Calibre PERC to typical ERC and ESD design scenarios.
  • Analyze both Spice netlists and chip layout data.