Tessent
Tessent MemoryBIST
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This course covers the Tessent Shell implementation flow of Tessent™ MemoryBIST. The Tessent™ MemoryBISTcourse will help you understand how to implement DFT for a memory test. You will be introduced to the Tessent Shell tool environment and instructed on how to utilize Tessent Shell to implement memory BIST solutions for your design. The lecture/lab format of the class gives you a conceptual understanding of how memory BIST circuitry for memories and IEEE 1687 (IJTAG) communication infrastructure can be automatically generated and inserted into a circuit.
Hands-on lab exercises will reinforce lecture and discussion topics.
Course Details
- Learn how to implement and validate MemoryBIST in your design.
- Basic knowledge of Verilog design
- Basic knowledge of manufacturing test generation flows. BIST experience is a plus
PRIMARY COURSE TOPICS
What You’ll Learn
- Setup your design for memory BIST and perform design rule checking
- Manage clock controllers, PLL, and clock dividers during memory BIST
- Utilize the DefaultsSpecifications and DftSpecifications for memory BIST implementations
- Generate and insert memory BIST IP and IEEE 1687 IP
- Verify the Tessent MemoryBIST implementation with simulation validations
- Utilize the PatternsSpecification to generate simulation validation patterns and ATE patterns
- Implement memory BIST with repairable memories, built-in self-repair, built-in repair analysis, and fuse boxes
- Specify and implement Tessent MemoryBIST at multiple levels in the hierarchy
- Implement Tessent BoundaryScan at the top level of the chip
Throughout this course, extensive hands-on lab exercises provide you with practical experience using Tessent software. Hands-on lab topics include:
- Demonstrate the flow for Tessent Boundary Scan, and Tessent MemoryBIST
- Labs focus on the flow and give you an example of some basic features of the Tessent IP
- The labs serve as a template for use when implementing DFT on a user-generated design