SystemVerilog
SystemVerilog UVM
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This course is for verification engineers who will be using UVM to code complex test benches and stimuli for digital designs. After completing this course, engineers will be able to build a complete UVM testbench from scratch, know the types of verification components in a UVM testbench, transaction-level modeling, the proper ways to use UVM phasing, and objections, UVM configuration, and how to build layered stimulus sequences.
Hands-on lab exercises reinforce lecture and discussion topics under the guidance of our industry expert instructors.
Prerequisites
- Familiarity with concepts of hardware verification.
- Knowledge of the SystemVerilog language, especially Object-Oriented Programming, randomization, and functional coverage.
Engineers should understand the new SystemVerilog design and verification features such as the new data types, interfaces, OOP, randomization, functional coverage, and interprocess communication.
Ideally, they should have applied these language features for several months on an actual project.
PRIMARY COURSE TOPICS
What You’ll Learn
- Overview of hardware verification
- Introduction to Universal Verification Methodology (UVM)
- UVM testbench architecture
- UVM test phases
- UVM objects and components
- UVM messaging
- UVM sequence items (transactions)
- Sequences of transactions
- Transaction Level Modeling (TLM)
- TLM ports, exports, and implementation exports
- UVM sequencers
- UVM drivers
- Emulation friendly drivers
- Sequence / driver synchronization
- TLM analysis ports, exports, and implementation exports
- UVM monitors
- UVM agents
- Coverage collectors
- Scoreboards and predictors
- UVM environments
- The UVM configuration database
- UVM factory
- UVM tests
- Virtual sequences
- Sequences for complex stimulus
- Sequencer arbitration
- Sequential and parallel sequences
- UVM register layer (Introduction)