This course is for verification engineers who will be using UVM to code complex test benches and stimuli for digital designs. After completing this course, engineers will be able to build a complete UVM testbench from scratch, know the types of verification components in a UVM testbench, transaction-level modeling, the proper ways to use UVM phasing, and objections, UVM configuration, and how to build layered stimulus sequences.
Hands-on lab exercises reinforce lecture and discussion topics under the guidance of our industry expert instructors.
Engineers should understand the new SystemVerilog design and verification features such as the new data types, interfaces, OOP, randomization, functional coverage, and interprocess communication.
Ideally, they should have applied these language features for several months on an actual project.