This course is for verification engineers who are using UVM to code complex test benches and stimuli for digital designs including registers and need to know more about the UVM Register Layer. After completing this course, engineers will be able to create and integrate the register model layer into their verification environment, use the register model to write reusable and maintainable sequences writing to the DUT, and gather functional coverage information about the register accesses.
Hands-on lab exercises reinforce lecture and discussion topics under the guidance of our industry expert instructors.