Tessent
Tessent Integrated Flow
Contact us for private event pricing
The Tessent Integrated Flow class is a high-level overview of the Tessent Integrated Flow. It is based upon using the Tessent Shell environment to run the Tessent family of tools to implement DFT, for both logic test and MemoryBist, in order to generate the test structures and test patterns necessary to properly test today’s SoCs.
Using the Tessent Shell integrated flow ties the process of inserting the test structures, which provide both controllability and observability of the internal nodes, into a design netlist and generating the patterns into a single environment. The tool has the capability of performing these functions on both flat and hierarchical designs, as well as for RTL and gate-level designs. The hierarchical capability provides an efficient and effective environment for design and development as the test patterns can be created as the hierarchical blocks are completed, then retargeted to the chip level.
Course Details
Learn how to leverage the Tessent Shell environment to insert logic and memory test structures into SoCs, generating and verifying the test patterns for ATE. This class is an overview of the Tessent Shell methodology and how to effectively and efficiently use different Tessent tools, such as Tessent Scan, Tessent MemoryBist, Tessent IJTAG, and others, work together in a flow and leverage the tools' output throughout the test structure insertion(e.g. scan, EDT, IJTAG, etc.) and ATPG process.
The in-depth details of using each individual tool are provided in our other course offerings which focus on the details and subtleties of different aspects of those specific tools. For example, if you are responsible for implementing memory tests in a design, the Tessent MemoryBIST course would be appropriate.
Hands-on lab exercises will reinforce lecture and discussion topics under the guidance of our industry expert instructors, These instructors can also provide guidance with respect to the tool courses which would be beneficial for you based upon your role in bringing the design to market.
- Familiarity with the basic concepts of SoC test methodologies and techniques, basics of memory organization and testing, JTAG, IJTAG, logic, and state devices.
There are no prerequisite courses as this course is an overview of the Tessent Shell flow. However, if you have taken other Tessent courses, this course will demonstrate how the different tools work together.
PRIMARY COURSE TOPICS
What You’ll Learn
- General overview of the DFT philosophy and flow using the Tessent tools to insert test structures and generate test patterns (ATPG) for SoCs
- JTAG and IJTAG (i.e. IEEE1149.1 and IEEE1687)
- Generation of ICL and PDL
- Performing DRC checks and debugging violations
- Understanding clocks, clocking, and Embedded Deterministic Test (EDT) concepts
- Implementing DFT from a flat design perspective
- Implementing DFT from a hierarchical perspective
- Implementing DFT for an RTL or gate-level design
- Insights as to how the Tessent Shell environment manages design data
- How to implement MBIST using Tessent DFT requirements, DFT Defaults Specification, and DFTSpecification
- How to implement Logic test using Tessent DFT requirements, DFT Defaults Specification, and DFTSpecification
- The generation, verification, and validation of tester patterns
- Retargeting patterns generated for lower-level design blocks to the chip level
Throughout this course, extensive hands-on lab exercises provide you with practical experience using Tessent Shell software. Hands-on lab topics include:
- Introduction to using the Tessent Shell which includes tool contexts, system modes, loading designs and libraries, design elaboration, and using commands to explore the tool and a design
- IJTAG, including ICL, PDL, creating and writing pattern sets, retargeting PDL, and accessing instruments on the IJTAG network
- Using Tessent MemoryBIST in the Tessent Shell flow, including how to work with different specifications used by the tool to generate test structures and patterns
- Insertion of a logic test using TestKompress
- Using a block-based bottom-up DFT flow within Tessent Shell
- Performing scan insertion including different scan modes, working with chain families, working with different wrappers, and working with wrapper chains and hierarchical blocks
Overview of running the Tessent ATPG process on flat and hierarchical designs, verifying generated patterns using a Verilog test bench, and retargeting patterns generated for a core such that they can be used on ATE
Insights as to how the Tessent Shell environment manages design data
- How to implement MBIST using Tessent DFT requirements, DFT Defaults Specification, and DFTSpecification
- How to implement Logic test using Tessent DFT requirements, DFT Defaults Specification, and DFTSpecification
- The generation, verification, and validation of tester patterns
- Retargeting patterns generated for lower-level design blocks to the chip level