Tessent Integrated Flow

Course Code
Tessent 2020.3
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6 hours for each day for 3 days

The Tessent Integrated Flow class is a high-level overview of the Tessent Integrated Flow. It is based upon using the Tessent Shell environment to run the Tessent family of tools to implement DFT, for both logic test and MemoryBist, in order to generate the test structures and test patterns necessary to properly test today’s SoCs.

Using the Tessent Shell integrated flow ties the process of inserting the test structures, which provide both controllability and observability of the internal nodes, into a design netlist and generating the patterns into a single environment. The tool has the capability of performing these functions on both flat and hierarchical designs, as well as for RTL and gate-level designs. The hierarchical capability provides an efficient and effective environment for design and development as the test patterns can be created as the hierarchical blocks are completed, then retargeted to the chip level.



  • Familiarity with the basic concepts of SoC test methodologies and techniques, basics of memory organization and testing, JTAG, IJTAG, logic, and state devices.

There are no prerequisite courses as this course is an overview of the Tessent Shell flow. However, if you have taken other Tessent courses, this course will demonstrate how the different tools work together.

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What You’ll Learn

  • General overview of the DFT philosophy and flow using the Tessent tools to insert test structures and generate test patterns (ATPG) for SoCs
  • JTAG and IJTAG (i.e. IEEE1149.1 and IEEE1687)
  • Generation of ICL and PDL
  • Performing DRC checks and debugging violations
  • Understanding clocks, clocking, and Embedded Deterministic Test (EDT) concepts
  • Implementing DFT from a flat design perspective
  • Implementing DFT from a hierarchical perspective
  • Implementing DFT for an RTL or gate-level design
  • Insights as to how the Tessent Shell environment manages design data
  • How to implement MBIST using Tessent DFT requirements, DFT Defaults Specification, and DFTSpecification
  • How to implement Logic test using Tessent DFT requirements, DFT Defaults Specification, and DFTSpecification
  • The generation, verification, and validation of tester patterns
  • Retargeting patterns generated for lower-level design blocks to the chip level