PRIMARY COURSE TOPICS

What You’ll Learn

• Introduction to SystemVerilog Assertions (SVA)**
  • A first look at SystemVerilog Assertions
  • The traditional design process
  • Using SVA in the definition of designs
  • Using SVA in the definition of verification
  • Using SVA to facilitate coverage metrics
  • Naming conventions
• Overview of SVA Properties and Sequences
  • Immediate and concurrent assertions
  • The SVA property construct
  • The SVA sequence construct
  • When to use properties versus sequences
  • Antecedent, consequent, and threads
  • Assertion, assumption, and verification directives
• Understanding Sequences
  • Sequence operators and built-in functions
  • Capturing temporal behavior
  • Implication operators
  • First match operator
  • Repetition operators
  • Sequence composition operators
  • Sequence methods
• Understanding Properties
  • Property declaration syntax
  • Using formal arguments
  • Local variables in properties
  • Clocking events
  • Disabling condition
  • Property expressions
  • Property operators
• Advanced Properties and Sequences
  • Data types in properties and sequences
  • Proper use of assertion overlapping
  • Chaining implication operators
  • Multiple thread termination
  • Unbounded ranges in properties
• SVA System Functions and System Tasks
  • Using the $sampled system function
  • Using the $past, $fell and $stable system functions
  • Vector analysis system functions
  • Severity level system functions
  • Assertion control system tasks
• Clocked and Multi-clocked Assertions
  • Clock specification for properties and sequences
  • Clock resolution
  • Using a default clock
  • Multiple clocked sequences
  • Multiple clocked properties
• Verification Directives & Verification-based Coverage
  • The assert, assume, and cover directives
  • SVA coverage
  • Coverage metrics
• Binding SVA to Design Blocks
  • The SVA bind construct
  • Binding to all instances of a module or interface
    • Binding to a single instance of a module or interface
    • Verifying VHDL models using SVA
• Assertion Verification Plans
  • What goes into an assertion verification plan
  • Planning the who, what, and where
  • Analyzing the design specification
  • Final project: Define assertions for a small RISC design