SystemVerilog
Visualizer Training
Course Code
281695-US
Software
SystemVerilog 2023.2
Language
English
User Level
All
Pricing ID
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List Price
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Live Online Duration
6 hours for each day for 2 days
The Visualzier course will help you to effectively use Visualizer™ Debug Environment to verify your design and explore your UVM based testbench.
PREREQUISITES
Prerequisites
- Familiarity with SystemVerilog class-based objects, and assertions
- Familiarity with VHDL, Verilog, SystemVerilog, and UVM (Universal Verification Methodology)
PROVIDED COURSE MATERIALS
Class Package
PRIMARY COURSE TOPICS
What You’ll Learn
- Invoke Visualizer in interactive and post-simulation modes
- Explore the most commonly used windows
- Save and load Visualizer debug session
- Search through your design environment
- Trace drivers and receivers
- Trace an X value in the simulation results using Time Cone Window
- View SystemVerilog Assertions in the GUI
- Debug SystemVerilog Assertions in the Assertion Thread Viewer (ATV)