The Tessent Streaming Scan Network class is an overview of the Tessent SSN tool used to create an efficient ATPG test data delivery system inside the integrated circuit. It is based upon using the Tessent Shell environment to run the Tessent family of tools to implement DFT in order to generate the test structures and test patterns necessary to properly test today’s SoCs.

Using the Tessent SSN tool in conjunction with the Tessent Shell integrated flow ties the process of inserting the test structures, providing both controllability and observability of the internal nodes, into a design netlist and generating the test patterns. The tool has the capability of performing these functions on both flat and hierarchical designs, as well as for RTL and gate-level designs. The hierarchical capability provides an efficient and effective environment for design and development as the test patterns can be created as the hierarchical blocks are completed, then retargeted to the chip level.