In this course you will learn about gate level netlist to GDSII flow in Aprisa. Starting with database initialization from input libraries , netlist, and timing constraints, you will learn how to set up up multi-mode , multi-corner timing analysis, create a floorplan and power mesh, perform placement optimization , clock tree synthesis , and routing optimization to achieve timing and DRC closure. At the end of the course, you will be able to use the Aprisa GUI to visualize the layout, perform timing analysis, cross-probe between timing reports and layout to identify timing closure issues, and browse DRC and LVS violations.
Familiarity with concepts of digital design
Basic Place and Route concepts
Statitc Timing Anslysis
What You’ll Learn
Throughout this course, extensive hands-on lab exercises provide you with practical experience using Aprisa software.
Hands-on lab topics include:
Aprisa GUI navigation
Initializing the design
Floorplanning and Power Planning
Clock Tree Synthesis