Aprisa
Aprisa

Course Code
288816-US
Software
Aprisa 21.R2
Language
English
User Level
All
List Price
$1,400.00 (USD)
Price may not include taxes applicable to your billing region
Training Center Duration
2 days

In this course you will learn about gate level netlist to GDSII flow in Aprisa. Starting with database initialization from input libraries , netlist, and timing constraints, you will learn how to set up up multi-mode , multi-corner timing analysis, create a floorplan and power mesh, perform placement optimization , clock tree synthesis , and routing optimization to achieve timing and DRC closure. At the end of the course, you will be able to use the Aprisa GUI to visualize the layout, perform timing analysis, cross-probe between timing reports and layout to identify timing closure issues, and browse DRC and LVS violations.

PREREQUISITES

Familiarity with concepts of digital design

Basic Place and Route concepts

Statitc Timing Anslysis

Power Analysis

DRC/LVS

PROVIDED COURSE MATERIALS
Class Package
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Learning Services, EDA USA

PRIMARY COURSE TOPICS

What You’ll Learn

Throughout this course, extensive hands-on lab exercises provide you with practical experience using Aprisa software.

Hands-on lab topics include:

Aprisa GUI navigation

Initializing the design

Floorplanning and Power Planning

Timing Analysis

Placement Optimization

Clock Tree Synthesis

Routing OptimizationAp