Solido DE
Solido Design Environment
Contact us for private event pricing
This course will introduce the students to the Solido™ Design Environment platform, which seamlessly integrates AI technology to perform production-accurate statistical yield analysis at a fraction of runtime, compared to brute-force methods, and assist the user in identifying optimization paths to improve circuit power, performance, and area. Solido™ Design Environment can be used throughout the design process, from initial device sizing to advanced 6+ sigma variation analysis.
After completing this course, the student will be able to use Solido™ Design Environment to set up SPICE-level simulations for circuit measurements and regressions, analyze waveforms and statistical results, and handle nominal and variation-aware analysis, all in a single cockpit.
Basic knowledge of AFS
PRIMARY COURSE TOPICS
What you’ll Learn
- Different features and licensing schemes of Solido™ Design Environment
- Solido™ Design Environment Graphical User Interface and Command-Line Interface
- Test setup and nominal simulation run with various flow models in Solido™ Design Environment
- Integrate Solido™ Design Environment with S-Edit, Siemens Custom IC design tool
- Feature the Back-Annotation and Cross-Probing from S-Edit Integration
- Custom outputs, scripted outputs, Interpretation of plots
- Solido™ Design Environment Data Management and Cluster Management
- Test groups, corner groups, and sweeps
- Key technologies in Solido™ Design Environment, including PVTMC Verifier, High-Sigma Monte Carlo, High Sigma Verifier, Hierarchical Monte Carlo, Fast PVT, DesignSense, and Cell Optimizer
- Creating Solido™ Design Environment reports and analyzing results in various flows
Throughout this course, extensive hands-on lab exercises provide you with practical experience using Solido™ Design Environment software. Hands-on lab topics include:
- Solido™ DE overview which introduces its Graphical user interface and command-line interface
- Test setup and simulation run in Solido™ DE core flow and netlist-in flow
- Experimenting with the hierarchy traversal when net listing using Config views in S-Edit
- Run DC Operating Points analysis to back-annotate the results back to the S-Edit tool
- Custom Output, which will focus on setting up and adding an executable custom output script that allows for the creation of compound measurements
- PVTMC Verifier, to determine the worst-case corners at target sigma for a target specification. High Sigma Monte Carlo, High Sigma Verifier, Hierarchical Monte Carlo, and Fast PVT tool to determine the output values at target sigma and DesignSense, Cell Optimizer to Optimize the designs