Tessent
Tessent ATPG Advanced Topics
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The Tessent™ ATPG advanced Topics course will drive the development of your skills and knowledge in advanced ATPG design utilizing the Tessent FastScan™, Tessent TestKompress, and the Tessent Visualizer tools. The course focuses on three key modules: advanced fault modes, low coverage debug, and simulation mismatch analysis. The knowledge gained for generating test patterns in this class is directly applicable for generating test patterns for designs utilizing Tessent™ TestKompress™. QuestaSim® is used to simulate test patterns to identify potential issues (mismatches) between the expected results from pattern generation and the Verilog simulation results. During this course, you will create high-quality test patterns using the ATPG tool.
The hands-on labs are designed to reinforce key concepts through practical experience and to develop proficiency with the Siemens EDA Tessent tool suite under the guidance of industry-expert instructors.
A basic background in DFT and Tessent ATPG Core Topics
PRIMARY COURSE TOPICS
What you will learn
- Generate ATPG patterns for a variety of advanced fault models.
- Identify and analyze blocks with low test coverage in your design.
- Use Tessent Visualizer to debug faults and investigate coverage issues. *Troubleshoot areas of low test coverage
- Troubleshoot simulation mismatches
Hands-on Labs
Throughout this course, extensive hands-on lab exercises provide you with practical experience using DFT software. Hands-on lab topics include:
- Generate ATPG patterns for a variety of advanced fault models.
- Identify and analyze blocks with low test coverage in your design.
- Classify untestable faults and determine the causes of ATPG Untestable (AU) faults.
- Use Tessent Visualizer to debug faults and investigate coverage issues.
- Troubleshoot areas of low test coverage
- Run both automated and manual simulation mismatch analysis in Tessent Shell, and debug mismatches using Tessent Visualizer and QuestaSim.