Tessent
Tessent ATPG Core Topics
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The Tessent™ ATPG Core Topics course will drive the development of your skills and knowledge in scan and ATPG design utilizing the Tessent Scan, Tessent FastScan™, and the Tessent Visualizer tools. The knowledge gained for generating test patterns in this class is directly applicable for generating test patterns for designs utilizing Tessent™ TestKompress™. QuestaSim® is used to simulate test patterns to identify potential issues (mismatches) between the expected results from pattern generation and the Verilog simulation results. During this course you will insert full scan in a design using Tessent Scan, and create high quality test patterns using the ATPG tool.
The hands-on lab exercises are designed to reinforce key concepts through practical experience and to develop proficiency with the Siemens EDA Tessent tool suite under the guidance of industry-expert instructors.
A basic background in DFT is helpful.
PRIMARY COURSE TOPICS
You will learn how to:
- Invoke the Tessent Shell environment in order to utilize Tessent Scan and Tessent FastScan
- Setup and analyze designs to prepare for ATPG
- Perform ATPG to achieve high test coverage with a minimal number of patterns
- Troubleshoot DRC violations
HANDS-ON LABS
Throughout this course, extensive hands-on lab exercises provide you with practical experience using DFT software. Hands-on lab topics include:
- Accessing documentation and getting help
- Using the scan and ATPG tool flow
- Reading and analyzing messages
- Troubleshooting a DRC error in Tessent Visualizer
- Using common methodologies to attain a quick estimate of test coverage
- Determining the cause of undetected faults
- Creating and saving patterns in different formats
- Reading ASCII files into Tessent FastScan
- Modifying timeplates
- Using different fault models and performing fault grading