Tessent
Tessent ATPG with TestKompress
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This course introduces Embedded Deterministic Test (EDT™) technology and Tessent TestKompress to engineers already familiar with Design-for-Test, but find that existing tools do not adequately deal with today’s aggressive design nodes. It is especially targeted towards those engineers working with ASIC/IC/SOC design projects where pattern size and test times are issues.
Hands-on labs are designed to reinforce key concepts through practical experience and to develop proficiency with the Tessent tool suite under the guidance of our industry-expert instructors.
Course Details
The hands-on lab exercises reinforce the lectures and provide useful examples of implementing EDT logic in their design to get the most benefits. Note: Students should be experienced with basic ATPG concepts prior to attending this class.
- A background in Design-for-Test
- The Tessent™ ATPG Core Topics training course
PRIMARY COURSE TOPICS
What You’ll Learn
- Use Tessent TestKompress in different EDT IP generation flows
- Calculate data compression and compression ratios
- Create Tessent TestKompress test patterns
- Troubleshoot common DRC violations
- Use EDT Finder for DRCs
- Use Test Points to improve compression
- Setup the TCD core modular flow
- Details of hierarchical test option
- Perform At-speed testing
- Simulate test patterns and troubleshoot mismatches
Throughout this course, extensive hands-on lab exercises provide you with practical experience using Tessent TestKompress software.
Hands-on lab topics include:
- Integrating Tessent TestKompress into Gate-level, RTL-level, and Modular Design Flows
- Exploring Tessent TestKompress Logic Features and Options
- Understanding and Troubleshooting Common DRC Violations
- Using EDT Finder
- Determining Compression and Performance
- Using Test Points to improve compression
- Using At-Speed Testing
- Debugging Simulation Mismatches
- Graphically Viewing Data and Troubleshooting Common DRCs