Designing a modern product requires the integration of multiple IP blocks from both in-house and third party sources. The Siemens EDA Tessent™ IJTAG solution delivers comprehensive automation support for implementing the IEEE 1687 standard, providing plug-and-play IP test and instrumentation integration.
The Tessent™ IJTAG Core Topics course drives the development of your skills and knowledge, using the Instrument Connectivity Language (ICL) in order to describe the interfaces and connectivity in your design. It also teaches you how to use the Procedural Description Language (PDL) in order to define operations applied to individual IP blocks. This course teaches you to extract the IJTAG ICL network data from the gate-level or RTL netlist; then uses these extracted networks to retarget PDL commands from the IP boundary to any point within an ICL-described IEEE 1687 Network.
The chip-level PDL commands can be translated to ATE pattern formats (STIL, WGL, and so on).
The hands-on labs are designed to reinforce key concepts through practical experience and to develop proficiency with Tessent IJTAG, and provide the basis for understanding the usage of IJTAG in the Tessent Integrated Flow under the guidance of industry-expert instructors.
The training course covers the basics required for Tessent MemoryBIST, Tessent ATPG with TestKompress, and Tessent SSN.
A basic background in DFT is helpful
Throughout this course, extensive hands-on lab exercises provide you with practical experience using Tessent software. Hands-on lab topics include: