Learning Center Overview and HyperLynx Curriculum 1  Chapter

Learn to navigate the Learning Center and view the HyperLynx curriculum.

1 Support Learning Center Overview and HyperLynx Curriculum 9 Topics

1. Support Learning Center Overivew
2. Video, Quiz, and Lab Times
3. System Engineer Curriculum Map
4. Digital Designer Curriculum Map
5. Signal Integrity Engineer Curriculum Map
6. PCB Designer Curriculum Map
7. EMI/EMC Analyst Curriculum Map
8. Model Librarian Curriculum Map
9. Package Designer Curriculum Map

Practical HyperLynx Methodology 6  Chapters

In this methodology-based learning path you will learn how to use HyperLynx to identify, analyze and solve design problems for optimum results.

1 Matching the HyperLynx Stackup with Vendor Datasheets 5 Topics

1. Matching the HyperLynx Stackup with Vendor Datasheets
2. Knowledge Check 1:Matching the HyperLynx Stackup with Vendor Datasheets
3. Factors Affecting Impedance for Single Ended and Differential Pairs
4. Knowledge Check 2:Matching the HyperLynx Stackup with Vendor Datasheets
5. Assessment:Matching the HyperLynx Stackup with Vendor Datasheets

2 Crosstalk Effects in Time and Frequency Domains 7 Topics

1. Crosstalk Effects in the Time Domain
2. Knowledge Check 1: Crosstalk Effects in Time and Frequency Domains
3. Coupling Effects in the Frequency Domain
4. Knowledge Check 2: Crosstalk Effects in Time and Frequency Domains
5. Common and Differential Crosstalk in the Frequency Domain
6. Knowledge Check 3: Crosstalk Effects in Time and Frequency Domains
7. Assessment: Crosstalk Effects in Time and Frequency Domains

3 Choosing the Right Termination 5 Topics

1. Fly-by Termination
2. Knowledge Check 1: Choosing the Right Termination
3. Source Series Termination Method
4. Knowledge Check 2: Choosing the Right Termination
5. Assessment Choosing the Right Termination

4 Managing Return Path Discontinuity at Signal Vias 7 Topics

1. Impact of Unmanaged Return Path Discontinuity
2. Knowledge Check 1: Managing Return Path Discontinuity at Signal Vias
3. Reducing Return Path Discontinuity for Planes at Same DC Voltage
4. Knowledge Check 2: Managing Return Path Discontinuity at Signal Vias
5. Reducing Return Path Discontunity for Planes of Different DC Voltages
6. Knowledge Check 3: Managing Return Path Discontinuity at Signal Vias
7. Assessment: Managing Return Path Discontinuity at Signal Vias

5 Designing Differential Vias on High-Speed Channels to Maximize Performance 7 Topics

1. Factors Affecting the Performance of a Differential Via
2. Knowledge Check 1: Designing Differential Vias on High-speed Channels to Maximize Performance
3. Determining the Maximum Via Stub Length
4. Knowledge Check 2: Designing Differential Vias on High-speed Channels to Maximize Performance
5. Optimizing Impedance of a Differential Via
6. Knowledge Check 3: Designing Differential Vias on High-speed Channels to Maximize Performance
7. Assessment: Designing Differential Vias on High-speed Channels to Maximize Performance

6 Identifying and Reducing Mode Conversion 7 Topics

1. Understanding Mode Conversion on Differential Pairs
2. Knowledge Check 1: Identifying and Reducing Mode Conversion
3. Mode Conversion Due to Skewed Buffer Model
4. Knowledge Check 2: Identifying and Reducing Mode Conversion
5. Mode Conversion Due to Asymmetric Interconnect
6. Knowledge Check 3: Identifying and Reducing Mode Conversion
7. Assessment: Identifying and Reducing Mode Conversion

HyperLynx DDRx Interface Analysis 7  Chapters

Learn how to effectively use the HyperLynx DDRx Wizard pre and post layout.

1 HyperLynx DDRx Interface Analysis Learning Path Overview 1 Topic

1. Learning Path Overview

2 Chapter 1: DDRx Primer and HyperLynx Overview 13 Topics

1. DDRx Primer: DDRx Architecture
2. Knowledge Check 1: DDRx Primer and HyperLynx Overview
3. DDRx Primer: Data Rates and Frequency
4. Knowledge Check 2: DDRx Primer and HyperLynx Overview
5. DDRx Primer: Signal Grouping and Direction
6. Knowledge Check 3: DDRx Primer and HyperLynx Overview
7. DDRx Primer: Timing and ODT Concepts - Part 1
8. DDRx Primer: Timing and ODT Concepts - Part 2
9. Knowledge Check 4: DDRx Primer and HyperLynx Overview
10. DDRx Primer: Topologies
11. Understanding the DDRx Design FlowUsing HyperLynx and Help
12. Knowledge Check 5: DDRx Primer and HyperLynx Overview
13. Assessment: DDRx Primer and HyperLynx Overview

3 Chapter 2 - Preparing for the DDRx Batch-Mode Wizard 9 Topics

1. DDRx Batch-Mode Wizard: LineSim Overview
2. Preparing for Pre-layout DDRx Batch-Mode Wizard - Single Board
3. Preparing for Pre-layout DDRx Batch-Mode Wizard - Multiboard
4. Knowledge Check 1: Preparing for the DDRx Batch-Mode Wizard
5. DDRx Batch-Mode Wizard - BoardSim Overview
6. Preparing for DDRx Batch-Mode Wizard - Post-layout
7. Knowledge Check 2: Preparing for the DDRx Batch-Mode Wizard
8. Lab : Preparing for the DDRx Batch-Mode Wizard
9. Assessment: Preparing to Use the DDRx Wizard

4 Chapter 3: Modeling DDRx Interfaces in HyperLynx 16 Topics

1. Stackups in LineSim
2. LineSim Via Models
3. Knowledge Check 1: Modeling DDRx Interfaces in HyperLynx
4. Stackups and Vias in BoardSim
5. Knowledge Check 2: Modeling DDRx Interfaces in HyperLynx
6. Physical DRAM Implementations
7. Knowledge Check 3: Modeling DDRx Interfaces in HyperLynx
8. IBIS Models
9. Knowledge Check 4: Modeling DDRx Interfaces in HyperLynx
10. S-Parameter Models
11. Knowledge Check 5: Modeling DDRx Interfaces in HyperLynx
12. Timing Models Part1
13. Timing Models Part2
14. Knowledge Check 6: Modeling DDRx Interfaces in HyperLynx
15. Lab: Modeling DDRx Interfaces in HyperLynx
16. Assessment: Modeling DDRx Interfaces in HyperLynx

5 Chapter4 - Running the DDRx Batch-Mode Wizard 23 Topics

1. DDR4 Technology Overview - Part 1
2. DDR4 Technology Overview - Part 2
3. DDR4 Technology Overview - Part 3
4. Knowledge Check 1: Running the DDRx Batch-Mode Wizard
5. Describing the Devices
6. Knowledge Check 2: Running the DDRx Batch-Mode Wizard
7. Interconnect Description - Part1
8. Interconnect Description - Part2
9. Knowledge Check 3: Running the DDRx Batch-Mode Wizard
10. Describing the Functionality and Timing
11. Knowledge Check 4: Running the DDRx Batch-Mode Wizard
12. WRITE/READ Leveling and Vref Training
13. Stimulus and Crosstalk
14. Knowledge Check 5: Running the DDRx Batch-Mode Wizard
15. Simulation Options and JEDEC Quality Checks
16. Report Options
17. Knowledge Check 6: Running the DDRx Batch-Mode Wizard
18. Common Set Up Issues
19. Simulation Results Files and Directories
20. Purpose of the DDRx Wizards in LineSim
21. Knowledge Check 7: Running the DDRx Batch-Mode Wizard
22. Lab: Verify Interface and Model Setup
23. Assessment: Running the DDRx Batch-Mode Wizard

6 Chapter5 - Analyzing DDR5 Interfaces 22 Topics

1. DDR5 Technology Overview
2. DDR5 Measurement Criteria
3. Vref Options For READ Cycles and Power Aware IBIS Models
4. Knowledge Check 1: Analyzing DDR5 Interfaces
5. DDR5 Analysis Tools Flows
6. DDR5 Analysis Flow Overview
7. Knowledge Check 2: Analyzing DDR5 Interfaces
8. Optimize DDR5 CA Bus and CS Signal - Methodology
9. Optimize DDR5 CA Bus and CS Signal - Methodology - Wizard
10. Knowledge Check 3: Analyzing DDR5 Interfaces
11. Design Methodology for the Data Bus
12. Optimizing DDR5 DQ Signals - Wizard
13. Optimizing DQS - Methodology
14. Optimizing DQS - EZwave
15. Knowledge Check 4: Analyzing DDR5 Interfaces
16. Byte Lane Verification - Methodology
17. Simulating Byte Lane WRITE and READ Cycles - Wizard
18. Byte Lane WRITE and READ Cycles - Simulation results
19. Knowledge Check 5: Analyzing DDR5 Interfaces
20. PDN Considerations
21. Knowledge Check 6: Analyzing DDR5 Interfaces
22. Assessment: Analyzing DDR5 Interfaces

7 HyperLynx DDRx Interface Analysis Exam 1 Topic

1. Level 1 Certification - HyperLynx DDRx Interface Analysis

HyperLynx Power Integrity and Thermal Analysis 9  Chapters

Learn how to use HyperLynx Power Integrity to detect problems and make corrections related to power planes and the thermal behavior of PCB designs.

1 HyperLynx Power Integrity and Thermal Analysis Learning Path Overview 1 Topic

1. Learning Path Overview

2 HyperLynx PI Overview 4 Topics

1. Analysis Strategies
2. Overview of HyperLynx Power Integrity Analysis
3. Knowledge Check 1: Overview and Analysis Strategies
4. Assessment : Overview and Analysis Strategies

3 DC Drop Analysis 19 Topics

1. Introduction to DC Drop Analysis
2. Post-layout DC Drop Analysis
3. The PowerScope
4. Knowledge Check 1: DC Drop Analysis
5. DC Drop Reports
6. Lab: Post Layout DC Drop Analysis
7. Exporting a PDN to LineSim
8. Lab: Exporting a Post Layout PDN to LineSim
9. Knowledge Check 2: DC Drop Analysis
10. Pre-Layout DC Drop Analysis
11. Lab: Pre-Layout DC Drop Analysis
12. Configuring DC Drop Batch Analysis
13. Knowledge Check 3: DC Drop Analysis
14. Running a DC Drop Batch Analysis
15. Simulating with Reference Nets
16. DC Drop Analysis in Xpedition Layout
17. Lab: DC Drop Batch Analysis
18. Knowledge Check 4: DC Drop Analysis
19. Assessment: DC Drop Analysis

4 Decoupling Analysis 32 Topics

1. Introduction to Decoupling Analysis
2. Decoupling Analysis Methodology
3. Understanding the PDN Impedance
4. Types of Decoupling Analysis
5. Knowledge Check 1: Decoupling Analysis
6. Modeling Decoupling Capacitors
7. Decoupling Analysis in the LineSim Environment
8. Placing Decoupling Capacitors in the LineSim Environment
9. Interactively Specifying Capacitors for Decoupling Analysis
10. Specifying Capacitor Models Using the QPL File
11. Knowledge Check 2: Decoupling Analysis
12. Running the Decoupling Wizard in LineSim Part 1
13. Running the Decoupling Wizard in LineSim Part 2
14. Running the Decoupling Wizard in LineSim - Demo
15. Understanding Quick Decoupling Analysis Results
16. Understanding Lumped Decoupling Analysis Results
17. Understanding Distributed Decoupling Analysis Results
18. Knowledge Check 3: Decoupling Analysis
19. Post Layout Decoupling Analysis Flow
20. Setting up Capacitors and Power Supplies for Post Layout Decoupling Analysis
21. Setting up Capacitors and Power Supplies for Post Layout Decoupling Analysis - Demo
22. Knowledge Check 4: Decoupling Analysis
23. Running a Post Layout Decoupling Analysis
24. Running a Post Layout Decoupling Analysis - Demo Part 1
25. Running a Post Layout Decoupling Analysis - Demo Part 2
26. Review PDN Design and Decoupling Capacitors
27. Lab: PDN Decopling Analysis
28. Knowledge Check 5: Decoupling Analysis
29. Signal Via Bypass Analysis
30. Lab: Signal Via Bypass
31. Knowledge Check 6: Decoupling Analysis
32. Assessment: Decoupling Analysis

5 Plane Noise Analysis 6 Topics

1. Plane Noise Analysis Concepts
2. Knowledge Check 1: Plane Noise Analysis Analysis
3. Plane Noise Analysis Demonstration
4. Lab: Plane Noise Analysis
5. Knowledge Check 2: Plane Noise Analysis
6. Assessment: Plane Noise Analysis

6 SI/PI Co-Simulation 11 Topics

1. The Need for SI/PI Co-Simulation
2. SI/PI Co-Simulation
3. SI/PI Co-Simulation - Demonstration
4. Lab: SI/PI Co-Simulation
5. Knowledge Check 1: SI/PI Co-Simulation
6. Power Aware IBIS Models
7. Simulating with Power Aware IBIS Models
8. SSO Analysis with Power Aware IBIS Models
9. Lab: Power Aware IBIS Models
10. Knowledge Check 2: SI/PI Co-Simulation
11. Assessment: SI/PI Co-Simulation

7 Model Extraction 5 Topics

1. Via Model Extraction
2. Knowledge Check 1: Via Model Extraction
3. PDN Model Extraction
4. Knowledge Check 2: PDN Model Extraction
5. Assessment: PDN Model Extraction

8 Thermal Analysis 15 Topics

1. Why Thermal Analysis?
2. Running Thermal Analysis
3. Knowledge Check 1: Thermal Analysis
4. Exporting Xpedition Layout Designs for Thermal Analysis
5. Exporting PADS Professional Layout Designs for Thermal Analysis
6. Thermal Libraries and Models
7. Knowledge Check 2: Thermal Analysis
8. The Thermal Environment
9. Improving Thermal Performance
10. Knowledge Check 3: Thermal Analysis
11. DC Drop and Thermal Co-Simulation
12. Resolving Settings and Library Problems
13. Lab: Thermal Simulation and DC Drop/Thermal Co-simulation
14. Knowledge Check 4: Thermal Analysis
15. Assessment : Thermal Analysis

9 HyperLynx Power Integrity & Thermal Analysis Exam 1 Topic

1. Level 1 Exam - HyperLynx Power Integrity & Thermal Analysis Exam

HyperLynx Signal Integrity Analysis 14  Chapters

In this course you will learn how to use HyperLynx to develop design constraints and to detect and correct signal integrity issues in your designs.

1 HyperLynx Signal Integrity Analysis Learning Path Overview 1 Topic

1. Learning Path Overview

2 HyperLynx SI Overview 12 Topics

1. The Roles of HyperLynx
2. HyperLynx Quickstart
3. Knowledge Check 1: HyperLynx SI Overview
4. Generating Design Constraints with LineSim
5. Developing Constraints in LineSim – A Solution
6. Analysis Strategies
7. Knowledge Check 2: HyperLynx SI Overview
8. HyperLynx SI Basics
9. Knowledge Check 3: HyperLynx SI Overview
10. HyperLynx User Interface
11. Knowledge Check 4: HyperLynx SI Overview
12. Assessment: HyperLynx SI Overview

3 LineSim User Interface 22 Topics

1. Creating LineSim Schematics
2. LineSim Graphical User Interface
3. Placing and Connecting Symbols
4. Knowledge Check 1: LineSim User Interface
5. Setting Up Model Libraries
6. Assigning Models
7. Knowledge Check 2: LineSim User Interface
8. Assigning Models
9. Assigning Series Passive Models
10. IC Component Models
11. Knowledge Check 3: LineSim User Interface
12. Stackup Manager
13. Stackup Editor
14. Stackup Advanced Considerations
15. Editing Stackups
16. Knowledge Check 4: LineSim User Interface
17. Digital Oscilloscope: Running Simulations
18. Digital Oscilloscope - Making Measurements
19. Knowledge Check 5: LineSim User Interface
20. SI Simulation with EZwave
21. Knowledge Check 6: LineSim User Interface
22. Assessment: LineSim User Interface

4 Interconnects 14 Topics

1. Lossless Transmission Lines
2. Knowledge Check 1: Transmission Lines
3. Uncoupled Transmission Lines in LineSim
4. Knowledge Check 2: Transmission Lines
5. Coupled Transmission Lines
6. Coupled Transmission Lines - Advanced Techniques
7. Configuring Coupled Transmission Lines
8. Knowledge Check 3: Transmission Lines
9. Reference Conductors
10. Vias and Padstacks
11. Vias: Simulating Via Configurations
12. Packaging
13. Knowledge Check 4: Transmission Lines
14. Assessment: Transmission Lines

5 Developing Constraints 20 Topics

1. Developing Constraints with LineSim
2. Knowledge Check 1: Developing Constraints
3. Technology
4. Knowledge Check 2: Developing Constraints
5. Topology
6. Knowledge Check 3: Developing Constraints
7. Termination
8. Terminator Wizard
9. Knowledge Check 4: Developing Constraints
10. Transmission Line Parameters
11. Investigating Trace Parameters
12. Knowledge Check 5: Developing Constraints
13. Exploring the Solution Space
14. Parametric Sweeps
15. Solution Space Exploration
16. Constraints
17. Performing a Termination Study
18. Pre-layout Flow
19. Knowledge Check 6: Developing Constraints
20. Assessment: Developing Constraints

6 BoardSim User Interface 11 Topics

1. Opening & Saving BoardSim Files
2. Working with Nets in BoardSim
3. Viewing Objects in BoardSim
4. Viewing Objects and Working with Nets in BoardSim
5. Knowledge Check 1: BoardSim User Interface
6. Assigning Models Using .REF & .QPL Files
7. Assiging Models Using .REF and .QPL Files
8. BoardSim Interactive Oscilloscope
9. BoardSim Interactive Crosstalk
10. Knowledge Check 2: BoardSim User Interface
11. Assessment: BoardSim User Interface

7 Batch Analysis in BoardSim 15 Topics

1. Analysis Wizards In Board Sim
2. Setting Up Quick Batch Analysis
3. Knowledge Check 1: Quick Batch Analysis
4. Examining Quick Batch Reports
5. Quick Batch Analysis
6. Detailed Batch Analysis Setup
7. Knowledge Check 2: Quick Batch Analysis
8. Crosstalk Related Settings
9. Knowledge Check 3: Quick Batch Analysis
10. Examining Detailed Batch Analysis Results
11. Interpreting Delay and Overshoot Results
12. Knowledge Check 4: Quick Batch Analysis
13. Detailed Batch Analysis
14. Knowledge Check 5: Quick Batch Analysis
15. Assessment: Quick Batch Analysis

8 Post-Layout Evaluation and Verification 11 Topics

1. HyperLynx Si Example Flow
2. Solving Post Layout SI Problems
3. Knowledge Check 1: Post-Layout Evaluation and Verification
4. Solving Post Layout Problems Through Routing Changes
5. Solving Post Layout Problems Using Quick Terminators
6. Solving SI Problems Using Quick Terminators
7. Knowledge Check 2: Post-Layout Evaluation and Verification
8. Solving Post Layout Problems Using Export to LineSim
9. Solving SI Problems Using Export to LineSim
10. Knowledge Check 3: Post-Layout Evaluation and Verification
11. Assessment: Post-Layout Evaluation and Verification

9 Exporting PCB Layouts to BoardSim 5 Topics

1. Preparing a Layout for BoardSim
2. Knowledge Check 1: Exporting PCB Layouts to BoardSim
3. Exporting a Layout to BoardSim
4. Knowledge Check 2: Exporting PCB Layouts to BoardSim
5. Assessment: Exporting PCB Layouts to BoardSim

10 Differential Pairs 13 Topics

1. Overview of Differential Pairs
2. Differential Pair Setup in BoardSim
3. Exploring Differential Pairs in BoardSim
4. Differential Pairs in BoardSim
5. Knowledge Check 1: Differential Pairs
6. Exploring Differential Pairs in LineSim
7. Exporting Differential Pairs to LineSim
8. Differential Pair Impedance Planning
9. Knowledge Check 2: Differential Pairs
10. Configuring Driver Stimulus
11. Differential Pairs in LineSim
12. Knowledge Check 3: Differential Pairs
13. Assessment: Differential Pairs

11 MultiBoard Analysis 14 Topics

1. MultiBoard Analysis Introduction
2. Knowledge Check 1: MultiBoard Analysis
3. Creating MultiBoard Projects
4. Knowledge Check 2: MultiBoard Analysis
5. Analyzing MultiBoard Projects
6. Knowledge Check 3: MultiBoard Analysis
7. Configuring Advanced Connectors in MultiBoard Projects
8. Simulating Advanced Connectors
9. Knowledge Check 4: MultiBoard Analysis
10. MultiBoard Analysis
11. Fixing SI and Crosstalk Problems
12. Working with Rigid-Flex Designs
13. Knowledge Check 5: MultiBoard Analysis
14. Assessment: MultiBoard Analysis

12 Theory, Simulation, and Measurements 17 Topics

1. Overview of High Speed Design Considerations
2. Knowledge Check 1: Theory, Simulation, and Measurements
3. Overshoot and Ringing
4. Reflections
5. Knowledge Check 2: Theory, Simulation, and Measurements
6. Measuring Overshoot
7. Simulating and Measuring Overshoot
8. Knowledge Check 3: Theory, Simulation, and Measurements
9. Timing Concepts
10. Timing Measurements
11. Timing Measurements
12. Knowledge Check 4: Theory, Simulation, and Measurements
13. Crosstalk Concepts
14. Simulating Crosstalk
15. EMI and HyperLynx DRC
16. Knowledge Check 5: Theory, Simulation, and Measurements
17. Assessment: Theory, Simulation, and Measurements

13 Models 15 Topics

1. Modeling ICs
2. Knowledge Check 1: Models
3. Testing IC Models
4. IBIS Package Wrapper
5. Knowledge Check 2: Models
6. S-Parameter Models
7. Using S-Parameter Models
8. SPICE Models
9. Knowledge Check 3: Models
10. Modeling Connectors and Packages
11. Modeling Passive Devices
12. Modeling Network Packs
13. Modeling Vias
14. Knowledge Check 4: Models
15. Assessment: Models

14 HyperLynx Signal Integrity Analysis Exam 1 Topic

1. Level 1 Exam - HyperLynx Signal Integrity Analysis

HyperLynx Serial Channel Design 6  Chapters

In this course, you will learn how to use the HyperLynx SerDes wizards with 2D and 3D modeling to design optimized serial channels.

1 HyperLynx Serial Channel Design Learning Path Overview 1 Topic

1. Learning Path Overview

2 SerDes Channel Design Theory 16 Topics

1. Methods of Data Transfer
2. SerDes Channel Background
3. HyperLynx SerDes Design Walk Through
4. Knowledge Check 1: SerDes Channel Overview
5. Signal Pre-conditioning: Tx
6. Signal Recovery: Rx
7. Lossy Transmission Lines
8. Knowledge Check 2: SerDes Channel Overview
9. SerDes Analysis Methods
10. Advantages of Protocol Compliance
11. Eye Diagram/Mask and BER/Bathtub Curves
12. Knowledge Check 3: SerDes Channel Overview
13. Channel Operating Margin - COM
14. Channel Operating Margin Simulation Reports
15. Knowledge Check 4: SerDes Channel Overview
16. Assessment: SerDes Channel Design Theory

3 SerDes Channel Design Flow Overview 9 Topics

1. SerDes Channel Design Process Overview
2. Progressive Design and Analysis
3. Supported Protocols
4. Knowledge Check 1: SerDes Channel Design Flow Overview
5. SerDes Compliance Check Wizard Overview
6. Verifying Compliance: Post Layout Overview
7. Knowledge Check 2: SerDes Channel Design Flow Overview
8. Lab: SerDes Channel Design Flow Overview
9. Assessment: SerDes Channel Design Flow Overview

4 Channel Design Process 15 Topics

1. Creating Representive Schematics in LineSim
2. IBIS/IBIS-AMI Models
3. S-Parameter Models
4. Package Models
5. Connector Models
6. Knowledge Check 1: Channel Design Process
7. Stackups
8. Vias
9. Via Stubs
10. HyperLynx Advanced Solver: LineSim 3D VIa Symbol
11. Exploring Crosstalk Effects
12. Backdrilling
13. Knowledge Check 2: Channel Design Process
14. Lab: Channel Design Process
15. Assessment: Channel Design Process

5 Board Level Compliance Verification 11 Topics

1. 3D Modeling Strategic Areas of a Board
2. 3D Modeling Demonstration
3. Postlayout SerDes Compliance Check Wizard
4. Postlayout SerDes Compliance Check Wizard Demonstration
5. Knowledge Check 1: Board Level Compliance Verification
6. Postlayout SerDes IBIS-AMI/S-Parameter Batch Wizard
7. Postlayout SerDes IBIS-AMI/S-Parameter Batch Wizard Demonstration
8. Signoff
9. Knowledge Check 2: Board Level Compliance Verification
10. Lab: Board Level Compliance Verification
11. Assessment: Board Level Compliance Verification

6 HyperLynx Serial Channel Design Exam 1 Topic

1. Level 1 Exam - HyperLynx Serial Channel Design

HyperLynx DRC 6  Chapters

Learn how to use HyperLynx DRC to analyze PCB designs to detect and correct EMI, SI, and power problems in designs.

1 HyperLynx DRC Learning Path Overview 1 Topic

1. Learning Path Overview

2 Introduction to HyperLynx DRC 8 Topics

1. Overview of HyperLynx DRC
2. HyperLynx DRC in the Design Flow
3. Knowledge Check 1: Introduction to HyperLynx DRC
4. HyperLynx DRC Methodology
5. Exporting PCB Data for HyperLynx DRC
6. Lab: Design Export
7. Knowledge Check 2: Introduction to HyperLynx DRC
8. Assessment: Introduction to HyperLynx DRC

3 HyperLynx DRC User Interface 8 Topics

1. Graphical User Interface
2. Project Explorer and Properties
3. Knowledge Check 1: HyperLynx DRC User Interface
4. Multi-Use Window
5. Board Viewer
6. Lab: User Interface
7. Knowledge Check 2: HyperLynx DRC User Interface
8. Assessment: HyperLynx DRC User Interface

4 Running HyperLynx DRC 13 Topics

1. Verification Flow
2. Project Data, Object Types, and Properties
3. Object Lists
4. Creating and Configuring Object Lists
5. Knowledge Check 1: Running HyperLynx DRC
6. Built-in Rules
7. Knowledge Check 2: Running HyperLynx DRC
8. Running Rules in HyperLynx DRC
9. Results, Reports, and ShareLists
10. Knowledge Check 3: Running HyperLynx DRC
11. Lab: Running HyperLynx DRC
12. Knowledge Check 4: Running HyperLynx DRC
13. Assessment: Running HyperLynx DRC

5 HyperLynx DRC Environment 13 Topics

1. The Options Menu
2. HyperLynx DRC Wizard
3. Locking Settings
4. Knowledge Check 1: HyperLynx DRC Environment
5. Models and Objects Overview
6. Assigning Models
7. Models in the Integrated Flow
8. Knowledge Check 2: HyperLynx DRC Environment
9. Settings Files
10. Lab: Project Setup Details
11. Knowledge Check 3: HyperLynx DRC Environment
12. Lab: HyperLynx DRC Project Challenge
13. Assessment: HyperLynx DRC Environment

6 HyperLynx DRC Exam 1 Topic

1. Level 1 Exam - HyperLynx DRC

HyperLynx Advanced Solvers 6  Chapters

Learn how to use HyperLynx Advanced Solvers to model 3D structures in PCB designs for use in detailed signal and power integrity analysis.

1 HyperLynx Advanced Solvers Learning Path Overview 1 Topic

1. Learning Path Overview

2 Introduction to HyperLynx Advanced Solvers 10 Topics

1. Introduction to HyperLynx Advanced Solvers Tool
2. Knowledge Check 1: Introduction to HyperLynx Advanced Solvers
3. Introduction to Hyperlynx 3D Field Solvers
4. Design Flow Integration in Hyperlynx Advanced Solvers
5. Knowledge Check 2: Introduction to HyperLynx Advanced Solvers
6. Project and Object Browsers
7. Navigating 3D Models and Viewing Features
8. Knowledge Check 3: Introduction to HyperLynx Advanced Solvers
9. Hyperlynx Advanced Solvers Interface Demo
10. Assessment: Introduction to HyperLynx Advanced Solvers

3 Setting Up Your First Project 6 Topics

1. Setting Up the First Project
2. Knowledge Check 1: Setting Up Your First Project
3. Setting Up Your First Project - Demo
4. Lab: Solving a Simple Differential Pair
5. Knowledge Check 2: Setting Up Your First Project
6. Assessment: Setting Up Your First Project

4 Advanced Solvers Concepts 10 Topics

1. Extracting Loop Inductance
2. Extracting Loop Inductance - Demo
3. Lab: Extracting Loop Inductance for a Power Supply Net
4. Knowledge Check 1: Advanced Solvers Concepts
5. Importing Circuit Models
6. Lab: Assigning a Circuit Model to a Component
7. Manually Creating Pins and Ports
8. Lab: Manually Create Pins and Ports
9. Knowledge Check 2: Advanced Solvers Concepts
10. Assessment: Advanced Solvers Concepts

5 3D Models and 3D Explorer 6 Topics

1. 3D Models
2. Knowledge Check 1: 3D Models and 3D Explorer
3. 3D Explorer and Sweeps
4. Sweep Simulations in 3D Explorer - Demo
5. Knowledge Check 2: 3D Models and 3D Explorer
6. Assessment: 3D Models and 3D Explorer

6 HyperLynx Advanced Solvers Exam 1 Topic

1. Level 1 Exam - HyperLynx Advanced Solvers

High Speed Signal Integrity Principles 8  Chapters

The High Speed Signal Integrity Principles course will help you properly manage the effects of high-speed signals on today’s PCB designs.

1 Learning Path Overview 2 Topics

1. Learning Path Overview
2. Virtual Lab Worsheet

2 Chapter 1 - Impedance and Stackup Design 11 Topics

1. Ground and Return Path
2. Time Delay and Impedance
3. Characterizing Transmission Lines
4. Lab: Impedance and Stackup - Exercises: 1-3
5. Knowledge Check 1: Impedance and Stackup Design
6. Signals on Transmission Lines
7. Lab: Impedance and Stackup - Exercises: 4-8
8. Eye Diagrams
9. Lab: Impedance and Stackup - Exercises: 9-10
10. Knowledge Check 2: Impedance and Stackup Design
11. Assessment: Impedance and Stackup Design

3 Chapter 2 - Reflections 13 Topics

1. Causes of Reflections
2. Knowledge Check 1: Reflections
3. Noise from Reflections and Terminations
4. Point to Point Routing
5. Knowledge Check 2: Reflections
6. Noise Margins
7. Lab 2: Reflections and Terminations - Exercises: 1-3
8. Charactersitics of Topologies
9. Lab 2: Reflections and Terminations - Exercises: 4-6
10. Impedance Discontinuities and Vias
11. Lab 2: Reflections and Terminations - Exercises: 7-9
12. Knowledge Check 3: Reflections
13. Assessment: Reflections

4 Chapter 3 - Crosstalk 6 Topics

1. Crosstalk Principles
2. Knowledge Check 1: Crosstalk
3. Crosstalk Waveforms: Near End and Far End
4. Lab 3: Crosstalk
5. Knowledge Check 2: Crosstalk
6. Assessment: Crosstalk

5 Chapter 4 - Differential Pairs 8 Topics

1. Differential and Common Signals
2. Differential and Common Impedance
3. Knowledge Check 1: Differerntial Pairs
4. Mode Conversion
5. Terminating Differential and Common Signals
6. Lab 4: Differential Pairs
7. Knowledge Check 2: Differential Pairs
8. Assessment: Differential Pairs

6 Chapter 5 - High-Speed Serial Link Channels and Loss 10 Topics

1. Losses, Reflection, Noise, and Mode Conversion
2. Skin Depth and Surface Roughness
3. Attenuation and Insertion Loss
4. Knowledge Check 1: High-Speed Serial Link Channels and Loss
5. Lab 5: High-Speed Serial Links and Losses - Exercises: 1-5
6. Designing to Minimize Mode Conversion
7. 1/4 Wave Stub Resonance
8. Lab 5: High-Speed Serial Links and Losses - Exercises: 6-8
9. Knowledge Check 2: High-Speed Serial Link Channels and Loss
10. Assessment: High-Speed Serial Link Channels and Loss

7 Chapter 6 - PDN Principles 9 Topics

1. Power Deliver Network Concepts
2. Decoupling
3. Knowledge Check 1: PDN Principles
4. Controlling PDN Impedance
5. Lab 6: Power Distribution Network - Exercises: 1-5
6. Vias Through Plane Cavities
7. Lab 6: Power Distribution Network - Exercises: 6-8
8. Knowledge Check 2: PDN Principles
9. Assessment: PDN Principles

8 High Speed Signal Integrity Principles Exam 1 Topic

1. Level 1 Exam - High Speed Signal Integrity Principles

HyperLynx DDR5 Interface Analysis 1  Chapter

You will learn the basics necessary to analyze a DDR5 interface.

1 HyperLynx DDR5 Interface Analysis 24 Topics

1. DDR5 Technology Overview
2. DDR5 Measurement Criteria
3. Vref Options For READ Cycles and Power Aware IBIS Models
4. Knowledge Check 1: DDR5 Interface Analysis
5. DDR5 Analysis Tools Flows
6. DDR5 Analysis Flow Overview
7. Knowledge Check 2: DDR5 Interface Analysis
8. Export the CA Bus and Chip Select and Running DDRx Batch-Mode Wizard Demonstration
9. Reviewing DDRx Wizard CA Bus and Chip Select Results Demonstration
10. Knowledge Check 3: DDR5 Interface Analysis
11. Design Methodology for the Data Bus
12. Setting up and Running the DDR5 Wizard Demonstration
13. Evaluating DDR5 Wizard Simulation Results Demonstration
14. Optimizing DQS
15. DQS Optimization Demonstration
16. Knowledge Check 4: DDR5 Interface Analysis
17. Byte Lane Verification
18. Simulating Byte Lane WRITE/READ Cycles Demonstration
19. Knowledge Check 5: DDR5 Interface Analysis
20. PDN Considerations
21. Advanced Decoupling Analysis Demonstration
22. Knowledge Check 6: DDR5 Interface Analysis
23. Lab : DDR5 Interface Analysis
24. Assessment

Teamcenter Share 1  Chapter

You will learn how Teamcenter Share fits into the Design Flow, its Configuration and Usage.

1 Teamcenter Share 8 Topics

1. Teamcenter Share Introduction
2. Teamcenter Share: Xpedition Workflow Example
3. Teamcenter Share Installation and Configuration
4. Knowledge Check: KC1
5. Teamcenter Share: Creating a Project
6. Teamcenter Share: Review and Markup
7. Knowledge Check: KC2
8. Assessment: System Designer User Interface

HyperLynx DRC Rule Writing 14  Chapters

In this course, you will learn how to use HyperLynx DRC to create a custom rule.

1 HyperLynx DRC Rule Writing Learning Path Overview 1 Topic

1. Learning Path Overview

2 Chapter 1: Introduction Scripting 1 Topic

1. Introduction Scripting

3 Chapter 2: Design Environment 1 Topic

1. Design Environment

4 Chapter 3: Anatomy of a Rule 2 Topics

1. Anatomy of a Rule
2. Starting a Custom Rule - Demo

5 Chapter 4: Automation Object Model 1 Topic

1. Automation Object Model

6 Chapter 5: Collections and Geometry Engines 1 Topic

1. Collections and Geometry Engines

7 Chapter 6: Field Solver 1 Topic

1. Field Solver

8 Chapter 7: Path Finder 1 Topic

1. Path Finder

9 Chapter 8: Graph Engine 1 Topic

1. Graph Engine

10 Chapter 9: Measure Engine 1 Topic

1. Measure Engine

11 Chapter 10: Violation Types and Action Scripts 1 Topic

1. Violation Types and Action Scripts

12 Chapter 11: Rule Documentation and Report 1 Topic

1. Rule Documentation and Report

13 Chapter 12: Rule Compiling and Testing 1 Topic

1. Rule Compiling and Testing

14 Chapter 13: External Automation 1 Topic

1. External Automation

HyperLynx Power Integrity Analysis 7  Chapters

Learn how to use HyperLynx PI to develop constraints and detect and correct DC and AC problems for the power delivery network(s) in your design.

1 HyperLynx Power Integrity Analysis Learning Path Overview 1 Topic

1. Learning Path Overview

2 Chapter 1 - HyperLynx PI Overview 8 Topics

1. Overview of HyperLynx Power Integrity Analysis
2. KC-1: HyperLynx PI Overview
3. DC Analysis Overview and Requirements
4. KC-2: HyperLynx PI Overview
5. AC Analysis Overview and Requirements
6. KC-3: HyperLynx PI Overview
7. Lab: HyperLynx PI Quickstart
8. Assessment: HyperLynx PI Overview

3 Chapter 2 - Modeling Requirements for DC and AC Analysis 8 Topics

1. Voltage Source Modeling
2. KC-1: Modeling Requirements for DC and AC Analysis
3. VRM Model Assignment in BoardSim
4. KC-2: Modeling Requirements for DC and AC Analysis
5. IC Power Pins Modeling
6. KC-3: Modeling Requirements for DC and AC Analysis
7. Lab: VRM Modeling
8. Assessment: Modeling Requirements for DC and AC Analysis

4 Chapter 3 - PDN Theory and Design Methodology 9 Topics

1. Introduction to PDN AC Analysis
2. KC-1: PDN Theory and Design Methodology
3. PDN Analysis Methodology - Part 1
4. KC-2: PDN Theory and Design Methodology
5. PDN Analysis Methodology - Part 2
6. KC-3: PDN Theory and Design Methodology
7. Understanding the PDN Impedance
8. KC-4: PDN Theory and Design Methodology
9. Assessment: PDN Theory and Design Methodology

5 Chapter 4 - Pre-layout Decoupling Analysis 25 Topics

1. Modeling Decoupling Capacitors
2. KC-1: Pre-layout Decoupling Analysis
3. Decoupling Analysis Types
4. KC-2: Pre-layout Decoupling Analysis
5. Pre-layout Decoupling Analysis
6. KC-3: Pre-layout Decoupling Analysis
7. Placing Decoupling Capacitors
8. KC-4: Pre-layout Decoupling Analysis
9. Assigning Decoupling Capacitor Models
10. KC-5: Pre-layout Decoupling Analysis
11. Running the Quick Analysis
12. KC-6: Pre-layout Decoupling Analysis
13. Placing the IC Power Pins and VRM
14. KC-7: Pre-layout Decoupling Analysis
15. Running the Lumped Analysis
16. KC-8: Pre-layout Decoupling Analysis
17. Running the Distributed Analysis - Part 1
18. KC-9: Pre-layout Decoupling Analysis
19. Running the Distributed Analysis - Part 2
20. KC-10: Pre-layout Decoupling Analysis
21. Running the Decoupling Analysis - Part 1
22. Running the Decoupling Analysis - Part 2
23. KC-11: Pre-layout Decoupling Analysis
24. Lab: Pre-layout Decoupling Analysis
25. Assessment: Pre-layout Decoupling Analysis

6 Chapter 5 - Post-layout Decoupling Analysis 12 Topics

1. Post-layout Decoupling Analysis
2. KC-1: Post-layout Decoupling Analysis
3. Decoupling Capacitors and Power Supplies in BoardSim
4. KC-2: Post-layout Decoupling Analysis
5. Decoupling Capacitors and Power Supplies in BoardSim - Demo
6. KC-3: Post-layout Decoupling Analysis
7. Running the Decoupling Analysis in BoardSim
8. KC-4: Post-layout Decoupling Analysis
9. PDN Design Recommendations and Guidelines
10. KC-5: Post-layout Decoupling Analysis
11. Lab: Post-layout Decoupling Analysis
12. Assessment: Post-layout Decoupling Analysis

7 Chapter 6 - DC Drop Analysis 16 Topics

1. Introduction to DC Drop
2. KC-1: DC Drop Analysis
3. Setting Up for DC Drop Analysis in BoardSim
4. KC-2: DC Drop Analysis
5. Running DC Drop in BoardSim
6. KC-3: DC Drop Analysis
7. Exporting to LineSim
8. KC-4: DC Drop Analysis
9. Simulating with Reference Nets
10. KC-5: DC Drop Analysis
11. Multi-phase VRMs and Sense Lines
12. KC-6: DC Drop Analysis
13. DC Drop with Shared Ground Currents
14. KC-7: DC Drop Analysis
15. Lab: DC Drop Analysis
16. Assessment: DC Drop Analysis

HyperLynx DRC Exam 1  Chapter

Test you skills and knowledge in HyperLynx DRC.

1 HyperLynx DRC Exam 1 Topic

1. Level 1 Exam - HyperLynx DRC

HyperLynx Signal Integrity Analysis Exam 1  Chapter

Demonstrate your skills and knowledge in HyperLynx Signal Integrity Analysis and earn a verifiable badge.

1 HyperLynx Signal Integrity Analysis Exam 1 Topic

1. Level 1 Exam - HyperLynx Signal Integrity Analysis

High Speed Signal Integrity Principles Exam 1  Chapter

Demonstrate your skills and knowledge in High-Speed Signal Integrity Principles and earn a verifiable badge.

1 High Speed Signal Integrity Principles Exam 1 Topic

1. Level 1 Exam - High Speed Signal Integrity Principles

HyperLynx Power Integrity & Thermal Analysis Exam 1  Chapter

Demonstrate your skills and knowledge in HyperLynx Power Integrity and Thermal Analysis and earn a verifiable badge.

1 HyperLynx Power Integrity & Thermal Analysis Exam 1 Topic

1. Level 1 Exam - HyperLynx Power Integrity & Thermal Analysis Exam

HyperLynx Advanced Solvers Exam 1  Chapter

Demonstrate your skills and knowledge in HyperLynx Advanced Solvers and earn a verifiable badge.

1 HyperLynx Advanced Solvers Exam 1 Topic

1. Level 1 Exam - HyperLynx Advanced Solvers

HyperLynx Serial Channel Design Exam 1  Chapter

Demonstrate your skills and knowledge in HyperLynx Serial Channel Design and earn a verifiable badge.

1 HyperLynx Serial Channel Design Exam 1 Topic

1. Level 1 Exam - HyperLynx Serial Channel Design

HyperLynx DDRx Interface Analysis Exam 1  Chapter

Demonstrate your knowledge of the basic methodologies and tool flow necessary to analyze DDRx interfaces and earn a verifiable badge.

1 HyperLynx DDRx Interface Analysis Exam 1 Topic

1. Level 1 Certification - HyperLynx DDRx Interface Analysis