learning path
Code Coverage
Explore how code coverage data is collected and analyzed in QuestaSim.
learning path
Functional Coverage
Explore how functional coverage data is collected and analyzed in QuestaSim.
learning path
Visualizer Coverage Debug
You will learn how to use Visualizer debug environment for code and functional coverage debug and analysis.
learning path
Advanced Verification for Verilog and VHDL
In this learning path you will learn how to add SystemVerilog Assertions and Functional Coverage to a Verilog or VHDL testbench.
learning path
UVM Testbench Generation
In this learning path you will learn how to use the code generator provided by the UVM Framework to generate UVM test benches.
On-Demand Training - Explore Questa Functional Verification
- 12 month subscription
- Access to cloud-based environment for hands-on lab exercises
- Access to new training content added during the subscription period
- Knowledge assessments to measure learning progress
Starting at
USD $500.00 / year
USD $500.00 / year