Learning Center Overview and Tanner EDA Curriculum 1  Chapter

Learn how to navigate the Mentor Learning Center and view a curriculum map for each user role.

1 Learning Center Overview and Tanner EDA Curriculum 4 Topics

1. Learning Center Overview
2. Video, Quiz, and Lab Times
3. MEMS Engineer
4. IC Engineer

Tanner Schematic Entry: S-Edit 9  Chapters

Learn how to leverage the power and sophistication of the Tanner Front-End tools to perform Schematic Entries, Project Structure and the creation of Schematics.

1 Tanner Front-End Core Concepts 6 Topics

1. Tanner Front-End Flow
2. Tanner Front-End Project Structure
3. Tanner Front-End Libraries and Cells Overview
4. Starting Up Tanner Tools
5. Lab 1: Introduction to Tanner Front-End Flow
6. Assessment: Tanner Front-End Core Concepts

2 Introduction to Tanner S-Edit 12 Topics

1. S-Edit GUI Overview
2. Adding Toolbars and Menus in S-Edit
3. Mouse Buttons, Locator and Status Toolbars in S-Edit
4. Creating and Opening Designs in S-Edit
5. Knowledge Check 1: Introduction to Tanner S-Edit
6. Cell and Hierarchy Navigators in S-Edit
7. Tanner S-Edit Technology Settings
8. Tanner S-Edit Preferences Settings
9. Saving and Loading Setup Files in S-Edit
10. Knowledge Check 2: Introduction to Tanner S-Edit
11. Lab 2: Introduction to Tanner S-Edit
12. Assessment: Introduction to Tanner S-Edit

3 Basic Cell Operations 12 Topics

1. Design Area Elements, Options and Controls in S-Edit
2. Creating, Opening and Traversing Cells in S-Edit
3. Cell Instantiation in S-Edit
4. Instance Properties in S-Edit
5. Knowledge Check 1: Basic Cell Operations
6. Cell and View Operations in S-Edit
7. Reserving Cells in S-Edit
8. Editing Tools in S-Edit
9. Using Strokes in S-Edit
10. Knowledge Check 2: Basic Cell Operations
11. Lab 3: Basic Cell Operations
12. Assessment: Basic Cell Operations

4 Design Tools and Features 10 Topics

1. Drawing Wires and Connections in S-Edit
2. Inserting Net Labels in S-Edit
3. Drawing and Labeling Ports in S-Edit
4. Knowledge Check 1: Design Tools and Features
5. Bundles, Buses and Arrays in S-Edit
6. Net Highlighting in S-Edit
7. Design Checking in S-Edit
8. Knowledge Check 2: Design Tools and Features
9. Lab 4: Design Tools and Features
10. Assessment: Design Tools and Features

5 Cells Symbols and Properties 14 Topics

1. Symbols Overview in S-Edit
2. Drawing Symbols in S-Edit
3. Inserting Text Labels and Ports in S-Edit
4. Knowledge Check 1: Cells Symbols and Properties
5. Adding Properties in S-Edit
6. Evaluated Properties in S-Edit
7. Properties Visibility in S-Edit
8. Knowledge Check 2: Cells Symbols and Properties
9. Export Control Properties in S-Edit
10. Global Nets in S-Edit
11. Inherited Connections in S-Edit
12. Knowledge Check 3: Cells Symbols and Properties
13. Lab 5: Cells Symbols and Properties
14. Assessment: Cells Symbols and Properties

6 Language Views in S-Edit 5 Topics

1. Creating Language Views in S-Edit
2. Language Design Checking in S-Edit
3. Generating Symbols in S-Edit
4. Lab 6: Cell Language Views in S-Edit
5. Assessment: Language Views in S-Edit

7 Automation in S-Edit 17 Topics

1. Command Window Options in S-Edit
2. Command Window Customization in S-Edit
3. Using Tcl Commands in S-Edit
4. Running Open Tcl Scripts in S-Edit
5. Knowledge Check 1: Automation in S-Edit
6. Running Tcl Scripts Automatically in S-Edit
7. Tcl Callbacks in S-Edit
8. Custom Command Buttons and Bind Keys in S-Edit
9. Setting Up Naming Constraints in S-Edit
10. Knowledge Check 2: Automation in S-Edit
11. Selective Evaluation Command in S-Edit
12. Annotating Ports Properties in S-Edit
13. Annotating Instances Properties in S-Edit
14. Evaluated Labels in S-Edit
15. Knowledge Check 3: Automation in S-Edit
16. Lab 7: Automation in S-Edit
17. Assessment: Automation in S-Edit

8 Exporting and Importing Designs 5 Topics

1. Capturing Designs Overview in S-Edit
2. SPICE Netlists Export and Import in S-Edit
3. Verilog Files Export and Import in S-Edit
4. Lab 8: Exporting and Importing Designs
5. Assessment: Exporting and Importing Designs

9 Tanner Schematic Entry: S-Edit Exam 1 Topic

1. Level 1 Certification - Tanner Schematic Entry: S-Edit

Tanner Front-End T-Spice Simulation Flow 3  Chapters

This learning path will help you gain the knowledge needed to harness the power of Tanner T-Spice & TWV in order to accurately simulate your analog ICs.

1 T-Spice Simulation Overview 18 Topics

1. Tanner Simulation Overview
2. Simulation Flow and Testbenches
3. Spice Simulation Setup in S-Edit
4. General Spice Simulation Setup
5. Using the Results Pane with T-Spice
6. Knowledge Check 1: T-Spice Simulation Overview
7. Tanner T-Spice Interface
8. Tanner Waveform Viewer Interface
9. Tanner Waveform Viewer: Charts and Plots
10. Tanner Waveform Viewer: Traces and Curves
11. Tanner Waveform Viewer: Waveform Calculator
12. Knowledge Check 2: T-Spice Simulation Overview
13. Lab 1.1: Introduction to Spice Simulation
14. Spice Netlisting
15. Simulation Log File
16. Knowledge Check 3: T-Spice Simulation Overview
17. Lab 1.2: Spice Netlisting
18. Assessment: T-Spice Simulation Overview

2 T-Spice Simulation Options 16 Topics

1. DC Operating Point Analysis
2. DC Sweep Analysis
3. AC Analysis
4. Transient Analysis
5. Knowledge Check 1: T-Spice Simulation Options
6. Lab 2.1: DC, AC and Transient Analysis
7. Monte Carlo Analysis
8. PVT Analysis
9. Knowledge Check 2: T-Spice Simulation Options
10. Lab 2.2: Monte Carlo and Corner Simulations
11. Noise Analysis
12. Parameter Sweep Analysis
13. Temperature Sweep Analysis
14. Knowledge Check 3: T-Spice Simulation Options
15. Lab 2.3 Noise, Parametric and Temperature Analysis
16. Assessment: T-Spice Simulation Options

3 Tanner T-Spice Simulation Flow Exam 1 Topic

1. Level 1 Exam - Tanner T-Spice Simulation Flow

Tanner Front-End AFS Simulation Flow 4  Chapters

Learn how to integrate Tanner front-end tool with AFS simulator to predict & verify the behavior & performance of the circuit using different types of analysis.

1 Simulation Setup 7 Topics

1. Tanner Simulation Overview
2. Tanner External Simulator Interface
3. Tanner Simulation Setup Window
4. Working with Netlists in S-Edit
5. Simulation Log File
6. Lab 1: Simulation Setup
7. Assessment: Simulation Setup

2 AFS Simulation Options 17 Topics

1. Simulation Flow and Testbenches
2. Properties and Testbench Settings
3. Simulation Performance Options
4. S-Edit Setup Simulation Results Pane
5. Knowledge Check 1: AFS Simulation Options
6. DC Operating Point Analysis
7. DC Sweep Analysis
8. Transient Analysis
9. AC Analysis
10. Knowledge Check 2: AFS Simulation Options
11. Lab 2.1: AFS Simulation Options - Part 1
12. PVT Analysis
13. Monte Carlo Analysis
14. Noise Analysis
15. Knowledge Check 3: AFS Simulation Options
16. Lab 2.2: AFS Simulation Options - Part 2
17. Assessment: AFS Simulation Options

3 EZwave Overview 6 Topics

1. EZwave Basic Capabilities
2. EZwave Measurement Tool and Cursors
3. EZwave Waveform Calculator
4. EZwave Parameter Table and Parameter Analyzer Tool
5. Lab 3: EZwave Overview
6. Assessment: EZwave Overview

4 Tanner AFS Simulation Flow Exam 1 Topic

1. Level 1 Exam - Tanner AFS Simulation Flow

Tanner Front-End Symphony Simulation Flow 4  Chapters

Learn how to integrate Tanner Front-End tool with Symphony mixed-signal simulator to simulate analog and digital designs exploiting AFS simulator's accuracy.

1 Symphony Overview 6 Topics

1. Mixed-Signal Simulation in Tanner Environment: Symphony Overview
2. Running a Simulation with Symphony
3. Boundary Elements Overview
4. Mixed-Signal Simulation Flow
5. Lab 1: Symphony Overview
6. Assessment: Symphony Overview

2 Using Symphony with Tanner 6 Topics

1. ADC8 Design Overview
2. Setting Up Symphony From S-Edit: Symphony Arguments
3. Setting Up Symphony From S-Edit: VSIM Simulation Settings
4. Setting Up Symphony From S-Edit: Boundary Elements
5. Lab 2: Using Symphony with Tanner
6. Assessment: Using Symphony with Tanner

3 Symphony Outputs 5 Topics

1. EZwave Output Waveforms
2. Boundary Elements in EZwave
3. Symphony Simulation Results
4. Lab 3: Symphony Outputs
5. Assessment: Symphony Outputs

4 Tanner Symphony Simulation Flow Exam 1 Topic

1. Level 1 Exam - Tanner Symphony Simulation Flow

Tanner Physical Layout: L-Edit Basic 8  Chapters

This learning path helps you gain knowledge of basic operations of L-Edit IC to perform physical designs of integrated circuits.

1 Introduction to Tanner Back-End Flow 11 Topics

1. Tanner Analog IC Back-End Flow
2. Tanner Back-End Project Structure
3. Tanner EDA Analog Full Design Flow Integration
4. Process Design Kits
5. Knowledge Check 1:Tanner IC Back End Flow
6. Starting Up Tanner Tools
7. GUI Overview
8. Toolbars Overview
9. Knowledge Check 2: Tanner IC Back End Flow
10. Lab: Introduction to Tanner Back End Flow
11. Assessment: Tanner IC Back End Flow

2 Design Creation 15 Topics

1. Starting A New Design in L-Edit
2. Attached VS. Referenced Libaries in L-Edit
3. OpenAccess vs. Tanner Database
4. Knowledge Check 1: Design Creation
5. Changing Tech Reference, Importing and Exporting Technology in L-Edit
6. L-Edit Setup Application: Configuration Files and General Settings
7. L-Edit Setup Application: Keyboard and Mouse Settings
8. Knowledge Check 2: Design Creation
9. L-Edit Setup Design: Technology Units, Resolution, and Grid
10. L-Edit Setup Design: Selection, Deselection and Edit Ranges
11. L-Edit Design Navigation
12. L-Edit Library & Cell Overview
13. Knowledge Check 3: Design Creation
14. Lab: Design Creation
15. Assessment: Design Creation

3 Cells Operations 16 Topics

1. Creating and Opening Cells
2. Cell Reservation
3. Knowledge Check 1: Cells Operations
4. Copying Cells
5. Instancing Cells: Introduction
6. Instancing Cells: Instance Replacement and Editing
7. Instancing Cells: Grouping, Ungrouping and Assigning Names of Instances
8. Renaming, Moving and Deleting Cells
9. Knowledge Check 2: Cells Operations
10. Additional Cell Operations
11. Customizing Library Navigator
12. Parameterized Cells
13. T-Cell Builder
14. Knowledge Check 3: Cells Operations
15. Lab: Cells Operations
16. Assessment: Cells Operations

4 Layers Operations 11 Topics

1. L-Edit: Layers and Layer Palette Overview
2. L-Edit: Custom Layer Palette
3. L-Edit: Setting Up Layers Part 1
4. L-Edit: Setting Up Layers Part 2
5. L-Edit: Setting Up Layers Part 3: Rendering
6. Knowledge Check 1: Layers Operations
7. L-Edit: Derivation Operations Overview
8. L-Edit: Layer Operations
9. Knowledge Check 2: Layers Operations
10. Lab: Layers Operations
11. Assessment: Layers Operations

5 Drawing Operations 16 Topics

1. Design Area Controls
2. L-Edit Status Bars
3. Drawing Toolbar
4. Knowledge Check 1: Drawing Operations
5. Drawing and Selecting Wires
6. Wires Utilities
7. Drawing Objects
8. Knowledge Check 2: Drawing Operations
9. L-Edit Ports and Labels
10. Drawing Presistent and Temporary Rulers
11. Generating Via Cells
12. Using Valid Vias for Assisted Routing
13. Object Boolean/Grow Operations
14. Knowledge Check 3: Drawing Operations
15. Lab: Drawing Operations
16. Assessment: Drawing Operations

6 Editing Operations 13 Topics

1. Editing Objects - Part 1
2. Editing Objects - Part 2
3. Knowledge Check 1: Editing Operations
4. Object Selection
5. Object Snapping
6. Manufacture Grid Snapping
7. Knowledge Check 2: Editing Operations
8. Object Alignment
9. Base Point Features
10. Layout Generator
11. Knowledge Check 3: Editing Operations
12. Lab: Editing Operations
13. Assessment: Editing Operations

7 Streaming In/Out Designs in L-Edit 6 Topics

1. Exporting Mask Data: GDSII Files
2. Importing Mask Data: GDSII Files
3. Importing and Exporting Mask Data: Gerber Files
4. Knowledge Check 1: Streaming
5. Lab: Streaming Designs
6. Assessment: Streaming Designs

8 Tanner Analog IC Design: L-Edit Basic Exam 1 Topic

1. Level 1 Certification - Tanner Analog IC Design: L-Edit Basic

Tanner Physical Verification: L-Edit Advanced 6  Chapters

This learning path helps you gain knowledge of advanced operations of L-Edit IC like SDL and Node Highlighting. You will also learn how to use Calibre One.

1 Advanced Layout Design 18 Topics

1. SDL Navigator Basics
2. Export SDL Using Export SPICE
3. Export SDL Using Publish to SDL
4. Lab 1.1: SDL - Publish to SDL
5. Load SDL Netlist in L-Edit
6. Lab 1.2: SDL - Netlist Driven Layout
7. Traversing Layout and Schematic
8. Lab 1.3: L-Edit and S-Edit Synchronization
9. Knowledge Check 1: Advanced Layout Design
10. Assisted Routing Features and Functions
11. Net-Specific Settings
12. Auto-Routing
13. Check Connectivity Function
14. Importing and Exporting LEF and DEF Files
15. Additional SDL Settings
16. Knowledge Check 2: Advanced Layout Design
17. Lab 1.4: Placement and Routing
18. Assessment: Advanced Layout Design

2 Built-in Automation Tools 10 Topics

1. Using Macros in L-Edit
2. Creating UPI Macro in L-Edit
3. Lab 2.1: UPI Macro
4. Knowledge Check 1: Automation
5. Guard Rings
6. Lab 2.2: Guard Rings
7. Built-In Macros: Mask Bias
8. Additional L-Edit Tools
9. Knowledge Check 2: Automation
10. Assessment: Automation

3 Rule-Aware Layout 6 Topics

1. Node Highlighting
2. Rule-Aware Layout
3. Geometry Flags
4. Knowledge Check1: Rule-Aware Layout
5. Lab 3: Node Highlighting & Geometry Flags
6. Assessment: Rule-Aware Layout

4 Design Rule Checking 9 Topics

1. Tanner Calibre One Integration
2. Calibre nmDRC Basic Concepts
3. Knowledge Check 1:DRC
4. Calibre Interactive nmDRC GUI: Loading Runsets
5. Calibre Interactive nmDRC: Running DRC
6. Interpreting DRC Results in RVE
7. Knowledge Check 2: DRC
8. Lab 4: Calibre DRC
9. Assessment: Design Rule Checking

5 Layout Vs. Schematic 10 Topics

1. Calibre nmLVS Basic Concepts
2. Calibre Interactive nmLVS Overview
3. Calibre Interactive nmLVS GUI: Rules, Inputs and Outputs Panes
4. Knowledge Check 1: LVS
5. Calibre Interactive nmLVS GUI: Options, Run Control and Transcript Panes
6. Interpreting LVS Results in RVE
7. Schematics Navigation in RVE
8. Knowledge Check 2: LVS
9. Lab 5: Calibre LVS
10. Assessment: LVS

6 Parasitic Extractions 10 Topics

1. Parasitic Extraction Basic Concepts
2. Calibre Interactive PEX Overview
3. Calibre Interactive PEX GUI: Rules, Inputs and Outputs Panes
4. Knowledge Check 1: PEX
5. Calibre Interactive PEX GUI: Options, Run Control and Transcript Panes
6. Interpreting PEX Results in RVE
7. Post-Layout Simulation
8. Knowledge Check 2: PEX
9. Lab 6: Calibre PEX
10. Assessment: PEX

L-Edit MEMS: Basic MEMS Layout 8  Chapters

Learn how to utilize the power of L-Edit to create, verify and stream in/out MEMS layout efficiently in the shortest time possible.

1 Introduction to Tanner L-Edit MEMS 9 Topics

1. Introduction to Tanner EDA L-Edit MEMS
2. Starting Up Tanner L-Edit MEMS
3. GUI Overview
4. Toolbars Overview
5. Knowledge Check 1: Introduction to Tanner L-Edit MEMS
6. L-Edit Application Settings
7. Knowledge Check 2: Introduction to Tanner L-Edit MEMS
8. Virtual Lab: Introduction to Tanner EDA L-Edit MEMS
9. Assessment: Introduction to Tanner L-Edit MEMS

2 Creating New Designs and Design Management 14 Topics

1. Creating New Design in L-Edit
2. OpenAccess and TDB Formats
3. L-Edit Technology Referencing Options
4. Knowledge Check 1: Creating New Designs and Design Management
5. Libraries and Design Navigators
6. Cell Operations - Part 1
7. Knowledge Check 2: Creating New Designs and Design Management
8. Virtual Lab: New Design Creation and Design Management
9. Cell Operations - Part 2
10. Cell Reservation
11. Design Area Controls and View Operations
12. Finding Objects
13. Knowledge Check 3: Creating New Designs and Design Management
14. Assessment: Creating New Designs and Design Management

3 Layout Design - Drawing 17 Topics

1. Introduction to Layers
2. Layer Palette Control
3. Layer Statuses in L-Edit
4. Knowledge Check 1: Layout Design - Drawing
5. Drawing Curved Shapes in L-Edit
6. Drawing Boxes, Wires and Polygons in L-Edit
7. Knowledge Check 2: Layout Design - Drawing
8. Object Selection
9. Measuring Distances Between Objects in L-Edit
10. Object Boolean/Grow Operations
11. Knowledge Check 3: Layout Design - Drawing
12. Object Snapping
13. Object Alignment
14. Using Base Points
15. Mouse Grid and Nudge Settings
16. Knowledge Check 4: Layout Design - Drawing
17. Assessment: Layout Design - Drawing

4 Layout Design - Editing 9 Topics

1. Editing Drawn Objects in L-Edit
2. Editing Instances in L-Edit
3. Editing Polygon Edges and Conversion Options
4. Editing Toolbar Commands
5. Curve Tools
6. Additional Editing Options
7. Editing Settings
8. Virtual Lab: Layout Design - Editing
9. Assessment: Layout Design - Editing

5 Derived Layers 11 Topics

1. Layer Setup
2. Knowledge Check 1: Derived Layers
3. Derived Layers Generation Procedure
4. Layer Derivation Procedure and Boolean Operations
5. Select Layer Derivation: Part 1
6. Select Layer Derivation: Part 2
7. Select Layer Derivation: Part 3
8. Density and Area Layer Derivations
9. Knowledge Check 2: Derived Layers
10. Virtual Lab: Derived Layers
11. Assessment: Derived Layers

6 Automation 12 Topics

1. Introduction to UPI
2. Creating and Editing Macros
3. Knowledge Check 1: Automation
4. Virtual Lab: Automation - Exercise 1
5. Introduction to T-Cells
6. Creating T-Cells
7. Knowledge Check 2: Automation
8. Layout Generators
9. Mask Bias
10. Knowledge Check 3: Automation
11. Virtual Lab: Automation - Exercise 2
12. Assessment: Automation

7 Verification and Streaming In/Out 17 Topics

1. Introduction to Verification
2. Knowledge Check 1: Verification and Streaming In/Out
3. Standard DRC Setup
4. Standard DRC Rules: Part 1
5. Standard DRC Rules: Part 2
6. Standard DRC Rules: Part 3
7. Geometry Flags
8. Knowledge Check 2: Verification and Streaming In/Out
9. Self-Intersection Fixing Techniques
10. The Verification Navigator
11. Virtual Lab: Verification and Streaming In/Out - Exercise 1
12. Exporting and Importing GDSII Files in L-Edit
13. Virtual Lab: Verification and Streaming In/Out - Exercise 2
14. Using DXF and EPS File Formats
15. Knowledge Check 3: Verification and Streaming In/Out
16. Virtual Lab: Verification and Streaming In/Out - Exercise 3
17. Assessment: Verification and Streaming In/Out

8 Tanner EDA L-Edit MEMS: Basic MEMS Layout Exam 1 Topic

1. Level 1 Certification Exam - Tanner EDA L-Edit MEMS: Basic MEMS Layout

Tanner Schematic Entry: S-Edit Exam 1  Chapter

Demonstrate your skills and knowledge in Tanner Analog IC Design Front-End tool “S-Edit” and earn a verifiable badge.

1 Tanner Schematic Entry: S-Edit Exam 1 Topic

1. Level 1 Certification - Tanner Schematic Entry: S-Edit

Tanner T-Spice Simulation Flow Exam 1  Chapter

Demonstrate your skills and knowledge in circuit verification using the Tanner T-Spice simulator and Tanner Waveform Viewer to earn a verifiable badge.

1 Tanner T-Spice Simulation Flow Exam 1 Topic

1. Level 1 Exam - Tanner T-Spice Simulation Flow

Tanner AFS Simulation Flow Exam 1  Chapter

Demonstrate your skills and knowledge in circuit verification using Analog FastSPICE (AFS) simulator from Tanner Front-End “S-Edit” tool and earn a badge.

1 Tanner AFS Simulation Flow Exam 1 Topic

1. Level 1 Exam - Tanner AFS Simulation Flow

Tanner Symphony Simulation Flow Exam 1  Chapter

Demonstrate your skills and knowledge in circuit verification using Symphony Mixed-Signal simulator from Tanner Front-End “S-Edit” tool.

1 Tanner Symphony Simulation Flow Exam 1 Topic

1. Level 1 Exam - Tanner Symphony Simulation Flow

Tanner Analog IC Design: L-Edit Basic Exam 1  Chapter

Earners of this badge have successfully completed the 25 question exam to show basic knowledge of physical layout using Tanner L-Edit.

1 Tanner Analog IC Design: L-Edit Basic Exam 1 Topic

1. Level 1 Certification - Tanner Analog IC Design: L-Edit Basic

Tanner Analog IC Design Layout Advanced Exam 1  Chapter

Demonstrate your skills and knowledge in Advanced Features of Tanner Analog Layout tool “L-Edit” and earn a verifiable badge.

1 Tanner Analog IC Design Layout Advanced Exam 1 Topic

1. Level 1 Certification - Tanner Analog IC Design Layout Advanced

Tanner EDA L-Edit MEMS: Basic MEMS Layout Exam 1  Chapter

Demonstrate your skills and knowledge in utilizing the power of L-Edit to create, verify and stream in/out MEMS layout efficiently and earn a verifiable badge.

1 Tanner EDA L-Edit MEMS: Basic MEMS Layout Exam 1 Topic

1. Level 1 Certification Exam - Tanner EDA L-Edit MEMS: Basic MEMS Layout