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On-Demand Training - Catapult High-Level Synthesis and Verification

The Catapult High-Level Synthesis (HLS) library contains a set of modules to introduce Engineers to HLS and High-Level Verification. To access this library for free, click buy and enter promotional code ExploreVEP__30 in the shopping cart.

12 month subscription
Access to cloud-based environment for hands-on lab exercises
Access to new training content added during the subscription period
Knowledge assessments to measure learning progress

Starting at
USD $2500.00 / year
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Learning Paths in "Catapult High-Level Synthesis and Verification"

Learning Paths provide guided chapters on a subject.

Chapters

learning path

Catapult Basic C++ and High-Level Synthesis

This learning path introduces engineers to C++, HLS and the use of Catapult for hardware design.

Preview Chapter

Module 1: A FIR Filter using Floating Point Data Types in C++

Catapult Basic C++ and High-Level Synthesis 14 Chapters

This learning path introduces engineers to C++, HLS and the use of Catapult for hardware design.

1 Module 1: A C++ Floating Point Finite Impulse Response Filter 4 Topics

Module 1: A FIR Filter using Floating Point Data Types in C++
Knowledge Check 1: A C++ Floating Point Finite Impulse Response Filter
Lab: A C++ Floating Point Finite Impulse Response Filter
Assessment: A C++ Floating Point Finite Impulse Response Filter

2 Module 2: Bit Accurate Datatypes (including fixed-point) 4 Topics

Module 2: Bit Accurate Datatypes for High-Level Synthesis
Knowledge Check: Bit Accurate Datatypes (including fixed-point)
Lab: Bit Accurate Datatypes (including fixed-point)
Assessment: Bit Accurate Datatypes (including fixed-point)

3 Module 3: Modify FIR Filter to use fixed-point 4 Topics

Module 3: Using Bit Accurate Datatypes in a FIR Filter
Knowledge Check: Modify FIR Filter to use fixed-point
Lab: Modify FIR Filter to use fixed-point
Assessment: Modify FIR Filter to use fixed-point

4 Module 4: Using Bit Accurate Datatypes in a FIR Filter 4 Topics

Module 4: Synthesizing the FIR Filter with Catapult
Knowledge Check: Using Bit Accurate Datatypes in a FIR Filter
Lab: Using Bit Accurate Datatypes in a FIR Filter
Assessment: Using Bit Accurate Datatypes in a FIR Filter

5 Module 5: Loop Constraints for Synthesis 4 Topics

Module5: Loop Constraints for Synthesis
Knowledge Check: Loop Constraints for Synthesis
Lab: Loop Constraints for Synthesis
Assessment: Loop Constraints for Synthesis

6 Module 6: Architectural Optimization 4 Topics

Module6: Architectural Optimization
Knowledge Check: Architectural Optimization
Lab: Architectural Optimization
Assessment: Architectural Optimization

7 Module 7: Data Streaming 4 Topics

Using ac_channels for Data Streaming in Catapult Designs
Knowledge Check 1: Module 7: Data Streaming
Lab: Module 7: Data Streaming
Assessment: Module 7: Data Streaming

8 Module 8: Creating a Hierarchical Design 4 Topics

Module 8 - Creating a Hierarchical Design
Knowledge Check 1: Module 8: Creating a Hierarchical Design
Lab: Module 8: Creating a Hierarchical Design
Assessment: Module 8: Creating a Hierarchical Design

9 Module 9: Using Memories in Catapult Designs 6 Topics

Module 9: Using Memories in Catapult Designs (Part 1)
Knowledge Check 1: Using Memories in Catapult Designs
Module 9: Using Memories in Catapult Designs (Part 2)
Knowledge Check 2: Using Memories in Catapult Designs
Lab: Using Memories in Catapult Designs
Assessment: Using Memories in Catapult Designs

10 Module 10: Using Shared Memories 4 Topics

Module 10: Using Shared Memories
Knowledge Check: Using Shared Memories
Lab: Using Shared Memories
Assessment: Using Shared Memories

11 Module 11: Examining IO Interfacing 4 Topics

Module 11: Examining IO Interfacing
Knowledge Check: Examining IO Interfacing
Lab: Examining IO Interfacing
Assessment: Examining IO Interfacing

12 Module 12: Memory Interfacing 4 Topics

Module 12: Memory Interfacing
Module 12: Knowledge Check
Module 12: Lab
Assessment: Memory Interfacing

13 Module 13: Pipelining Constraints 4 Topics

Module 13: Pipelining Constraints
Module 13: Knowledge Check
Module 13: Lab
Assessment: Pipelining Constraints

14 Module 14: Loop Merging 4 Topics

Module 14: Loop Merging
Module 14: Knowledge Check
Module 14: Lab
Assessment: Loop Merging

Chapters

learning path

Design and Verification Using SystemC and MatchLib

This learning path introduces users to the design concepts needed for HLS design, debug, and verification using SystemC and the MatchLib library.

Preview Chapter

Module 1.1: HLS Synthesis of SystemC Designs

Design and Verification Using SystemC and MatchLib 6 Chapters

This learning path introduces users to the design concepts needed for HLS design, debug, and verification using SystemC and the MatchLib library.

1 Module 1: Modeling Datapath Interfaces in SystemC 8 Topics

Prerequisite Material for Module 1
Module 2: Bit Accurate Datatypes
Lab: Bit Accurate Datatypes (including fixed-point)
Module 1.1: HLS Synthesis of SystemC Designs
Module 1.2: “RTL in SystemC” coding style
Module 1.3: What is MatchLib?
Module 1.4: Using the MatchLib Connections Library
Lab: Module 1

2 Module 2: Automated SystemC to RTL Verifcation 1 Topic

Module 2: Automated SystemC to RTL verification

3 Module 3: Basic Interface Protocols and Hardware Behavior 2 Topics

Module 3: Basic Interface Protocols and Hardware Behavior
Lab: Module 3

4 Module 4: Loop Unrolling and Pipelining 4 Topics

Prerequisite Material for Module 4
Module 5: Loop Unrolling and Pipelining
Module 13: Pipelining Constraints
Lab: Module 4

5 Module 5: Arrays and Memories 3 Topics

Prerequisite material for Module 5
Module 9: Using Memories in Catapult Designs
Lab: Module 5

6 Module 6: Multi-Block Design Using SystemC and MatchLib 5 Topics

Module 6.1: Communication Between Threads and Modules
Module 6.2: FIFO Interconnect
Module 6.3: Shared Memories
Module 6.4: Configuration Status Registers
Lab: Module 6

Chapter

learning path

Learning Center Overview and Catapult Curriculum

Learn how to navigate the Mentor Learning Center and view a curriculum map for each user role.

Preview Chapter

Learning Center Overview

Chapter

learning path

High-Level Verification

This learning path introduces users to the Catapult HLV flow, enabling rigorous functional verification of high-level source using known and trusted techniques.

Preview Chapter

HLV Introduction

4 Learning Paths

28 Chapters

104 Topics

4 Hours of Video

Library Outline

Receive unlimited access to all new content added during your active subscription.

During your subscription period, you will automatically receive access to all new content added to the library, including training on new product releases and technology updates to maximize your proficiency.

On-Demand Training - Catapult High-Level Synthesis and Verification

12 month subscription
Access to cloud-based environment for hands-on lab exercises
Access to new training content added during the subscription period
Knowledge assessments to measure learning progress

Starting at
USD $2500.00 / year

Buy

Change this page to

On-Demand Training - Catapult High-Level Synthesis and Verification

Learning Paths in "Catapult High-Level Synthesis and Verification"

Catapult Basic C++ and High-Level Synthesis

Module 1: A FIR Filter using Floating Point Data Types in C++

Catapult Basic C++ and High-Level Synthesis 14 Chapters

1 Module 1: A C++ Floating Point Finite Impulse Response Filter 4 Topics

2 Module 2: Bit Accurate Datatypes (including fixed-point) 4 Topics

3 Module 3: Modify FIR Filter to use fixed-point 4 Topics

4 Module 4: Using Bit Accurate Datatypes in a FIR Filter 4 Topics

5 Module 5: Loop Constraints for Synthesis 4 Topics

6 Module 6: Architectural Optimization 4 Topics

7 Module 7: Data Streaming 4 Topics

8 Module 8: Creating a Hierarchical Design 4 Topics

9 Module 9: Using Memories in Catapult Designs 6 Topics

10 Module 10: Using Shared Memories 4 Topics

11 Module 11: Examining IO Interfacing 4 Topics

12 Module 12: Memory Interfacing 4 Topics

13 Module 13: Pipelining Constraints 4 Topics

14 Module 14: Loop Merging 4 Topics

Design and Verification Using SystemC and MatchLib

Module 1.1: HLS Synthesis of SystemC Designs

Design and Verification Using SystemC and MatchLib 6 Chapters

1 Module 1: Modeling Datapath Interfaces in SystemC 8 Topics

2 Module 2: Automated SystemC to RTL Verifcation 1 Topic

3 Module 3: Basic Interface Protocols and Hardware Behavior 2 Topics

4 Module 4: Loop Unrolling and Pipelining 4 Topics

5 Module 5: Arrays and Memories 3 Topics

6 Module 6: Multi-Block Design Using SystemC and MatchLib 5 Topics

Learning Center Overview and Catapult Curriculum

Learning Center Overview

Learning Center Overview and Catapult Curriculum 1 Chapter

1 Learning Center Overview and Catapult Curriculum 2 Topics

High-Level Verification

HLV Introduction

High-Level Verification 1 Chapter

1 High-Level Verification Introduction 3 Topics

On-Demand Training - Catapult High-Level Synthesis and Verification

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mouse On-Demand Training - Catapult High-Level Synthesis and Verification

Learning Paths in "Catapult High-Level Synthesis and Verification"

Catapult Basic C++ and High-Level Synthesis

Module 1: A FIR Filter using Floating Point Data Types in C++

Catapult Basic C++ and High-Level Synthesis 14 Chapters

1 Module 1: A C++ Floating Point Finite Impulse Response Filter 4 Topics

2 Module 2: Bit Accurate Datatypes (including fixed-point) 4 Topics

3 Module 3: Modify FIR Filter to use fixed-point 4 Topics

4 Module 4: Using Bit Accurate Datatypes in a FIR Filter 4 Topics

5 Module 5: Loop Constraints for Synthesis 4 Topics

6 Module 6: Architectural Optimization 4 Topics

7 Module 7: Data Streaming 4 Topics

8 Module 8: Creating a Hierarchical Design 4 Topics

9 Module 9: Using Memories in Catapult Designs 6 Topics

10 Module 10: Using Shared Memories 4 Topics

11 Module 11: Examining IO Interfacing 4 Topics

12 Module 12: Memory Interfacing 4 Topics

13 Module 13: Pipelining Constraints 4 Topics

14 Module 14: Loop Merging 4 Topics

Design and Verification Using SystemC and MatchLib

Module 1.1: HLS Synthesis of SystemC Designs

Design and Verification Using SystemC and MatchLib 6 Chapters

1 Module 1: Modeling Datapath Interfaces in SystemC 8 Topics

2 Module 2: Automated SystemC to RTL Verifcation 1 Topic

3 Module 3: Basic Interface Protocols and Hardware Behavior 2 Topics

4 Module 4: Loop Unrolling and Pipelining 4 Topics

5 Module 5: Arrays and Memories 3 Topics

6 Module 6: Multi-Block Design Using SystemC and MatchLib 5 Topics

Learning Center Overview and Catapult Curriculum

Learning Center Overview

Learning Center Overview and Catapult Curriculum 1 Chapter

1 Learning Center Overview and Catapult Curriculum 2 Topics

High-Level Verification

HLV Introduction

High-Level Verification 1 Chapter

1 High-Level Verification Introduction 3 Topics

mouse On-Demand Training - Catapult High-Level Synthesis and Verification

On-Demand Training - Catapult High-Level Synthesis and Verification

On-Demand Training - Catapult High-Level Synthesis and Verification