Learning Center Overview and Tessent Curriculum 1  Chapter

Learn how to navigate the Learning Center and view a curriculum map for each user role.

1 Learning Center Overview and Tessent Training Library Curriculum 4 Topics

1. Learning Center Overivew
2. Video, Quiz, and Lab Times
3. Engineer
4. Manager

Getting Help With Tessent Tools 1  Chapter

You will learn how to access infohub, get help within Tessent tools and use the Support Center.

1 Getting Help 6 Topics

1. Getting Help: Using Infohub
2. Getting Help: Within Tessent Tools
3. Getting Help: Using the Support Center
4. Knowledge Check 1: Getting Help
5. Lab: Exploring the Help System
6. Assessment Getting Help

Tessent Scan and ATPG 13  Chapters

This learning path will introduce you to scan and ATPG processes. You will gain knowledge on fault models, test pattern types and at-speed testing.

1 DFT Basic Concepts 11 Topics

1. DFT Motivations
2. Introduction to Scan Test and ATPG
3. Basic Scan Test Process
4. Knowledge Check 1: DFT Basic Concepts
5. Getting Started with Tessent Shell
6. Understanding Contexts and System Modes
7. Design Objects, Attributes and Data Models
8. Creating and Using Collections
9. Design Introspection
10. Knowledge Check 2: DFT Basic Concepts
11. Assessment: DFT Basic Concepts

2 Scan and Test Insertion 21 Topics

1. Tessent Scan Tool Flow Overview
2. Tessent Scan Setup
3. Scan/Test Logic Configurations
4. Knowledge Check 1: Scan and Test Insertion
5. Scan Design Rule Checks
6. Scan/Test Logic Insertion
7. Defining Scan Modes
8. Knowledge Check 2: Scan and Test Insertion
9. Balanced Scan Chains
10. Multi-Mode Scan Insertion
11. Tessent Scan TSDB FLow
12. Knowledge Check 3: Scan and Test Insertion
13. Introduction to VersaPoints Test Points
14. Inserting Test Points
15. Hierarchical DFT Flow Overview
16. Wrapper Chains Overview
17. Wrapper Chains Generation
18. Grayboxes Overview
19. Knowledge Check 4: Scan and Test Insertion
20. Lab: Configuring Scan Chains / Test Logic
21. Assessment: Scan and Test Insertion

3 The ATPG Flow 15 Topics

1. DFT Flow in Tessent Shell
2. Creating DFT Library
3. Defining Black Boxes
4. Knowledge Check 1: The ATPG Flow
5. ATPG Setup: Test Procedure Files
6. ATPG Setup: Dofiles
7. DC Scan Insertion Flow
8. Knowledge Check 2: The ATPG Flow
9. ATPG Setup Process
10. ATPG DRC Process
11. Configuring ATPG and Generating Patterns Process
12. ATPG Save Results Process
13. Knowledge Check 3: The ATPG Flow
14. Lab: Generating Test Patterns
15. Assessment: The ATPG Flow

4 Fault Grouping, Coverage and Transcripts 11 Topics

1. Defining the Fault Universe
2. Fault Classes: The Testable Faults (Part 1)
3. Fault Classes: The Testable Faults (Part 2)
4. Fault Classes: The Untestable Faults
5. Knowledge Check 1: Faults Grouping
6. Fault Subclasses
7. Test Coverage Reporting
8. Tessent Transcript / Logfile Overview
9. Knowledge Check 2: Faults Grouping
10. Lab: Understanding ATPG Messaging
11. Assessment: Faults Grouping

5 Additional Fault Models 21 Topics

1. The Bridge Fault Model
2. At-Speed Testing: The Transition Fault Model
3. At-Speed Testing: The Path Delay Fault Model
4. Knowledge Check 1: Additional Fault Models
5. User Defined Fault Model (UDFM)
6. Cell-Aware Model Overview
7. IDDQ Fault Model
8. Knowledge Check 2: Additional Fault Models
9. Toggle Fault Model
10. Automotive-Grade ATPG
11. Interconnect Bridge Defects
12. Knowledge Check 3: Additional Fault Models
13. Interconnect Open Defects
14. Cell Neighboring Bridge Defects
15. Automotive-Grade ATPG and Dignosis Flow
16. Critical Area Calculations
17. Timing-Aware ATPG Overview
18. Timing-Aware ATPG Details
19. Knowledge Check 4: Additional Fault Models
20. Lab: Additional Fault Models
21. Assessment: Additional Fault Models

6 Additional Test Pattern Types 7 Topics

1. Clock Sequential Patterns Overview
2. Clock Sequential Pattern Operation
3. Knowledge Check 1: Additional Test Pattern Types
4. Testing Around RAMs
5. Multiple Load Patterns
6. Knowledge Check 2: Additional Test Pattern Types
7. Assessment: Additional Test Pattern Types

7 Test Patterns Management 5 Topics

1. Generating and Reporting Test Patterns
2. Reusing and Debugging Patterns
3. Verification and Manufacturing Patterns
4. Lab: Understanding Test Pattern Generation
5. Assessment: Test Patterns Management

8 At-Speed Patterns and OCC 16 Topics

1. Transition Fault Model Detection
2. Path Delay Fault Model Detection
3. Knowledge Check 1: At-Speed Patterns and OCC
4. At-Speed Pattern Generation: Using Launch-Off-Capture/Broadside
5. At Speed Pattern Generation: Using Launch-Off-Shift
6. Fault Grading Patterns
7. Knowledge Check 2: At-Speed Patterns and OCC
8. Generating Internal Clocks
9. OCC Overview
10. Clock Control Definitions
11. Clock Control Definitions With ATPG
12. Named Capture Procedure
13. NCP Patterns Verification
14. Knowledge Check 3: At-Speed Patterns and OCC
15. Lab:Testing for High Quality
16. Assessment: At-Speed Patterns and OCC

9 Design Rule Overview 16 Topics

1. Flat Model Creation
2. ATPG Design Rule Checking
3. C1 Design Rule Check
4. C3/C4 Design Rule Checks
5. Knowledge Check 1: DRC
6. C6 Design Rule Check
7. D1 Design Rule Check
8. D5/D6 Design Rule Checks
9. E4 /E5 / E10 Design Rule Checks
10. Knowledge Check 2: DRC
11. Scan Chain Trace Rules
12. DRC Viewing
13. DRC Debugging Using Gate Reporting
14. Knowledge Check 3: DRC
15. Lab:Troubleshooting DRCs
16. Assessment: DRC

10 Troubleshooting Low Test Coverage 13 Topics

1. Identifying Sources and Areas of Low Coverage
2. Analyzing Faults in Tessent Visualizer
3. Knowledge Check 1: Troubleshooting Low Coverage
4. Analyzing Causes of Low Coverage: The Stuck-at-Faults
5. Analyzing Causes of Low Coverage: The Aborted Faults
6. Debugging Uncontrolled Faults
7. Debugging ATPG Untestable Faults
8. Knowledge Check 2: Troubleshooting Low Coverage
9. Debugging Transition and Path Delay Faults
10. ATPG Event Simulation
11. Knowledge Check 3: Troubleshooting Low Coverage
12. Lab: Troubleshooting Low Coverage
13. Assessment: Troubleshooting Low Coverage

11 Simulation Mismatch 21 Topics

1. Introduction to Simulation Mismatch
2. Parallel vs. Serial Testbench
3. Knowledge Check 1: Simulation Mismatch
4. Verilog Testbenches
5. Parallel Testbenches
6. Serial Testbenches
7. Knowledge Check 2: Simulation Mismatch
8. Simulation Mismatches Debugging: Obtaining Debug Files
9. Simulation Mismatches Debugging: Extracting Information
10. Simulation Mismatches Debugging: Tracing Back
11. Knowledge Check 3: Simulation Mismatch
12. Possible Mismatch Causes: Timing
13. Possible Mismatch Causes: CDD/NCP and Internal Pins
14. Possible Mismatch Causes: DRC
15. Knowledge Check 4: Simulation Mismatch
16. Possible Mismatch Causes: Library Problems
17. Simulation Mismatches Debugging: Implementing Solutions
18. Automatic Simulation Mismatch Analysis Flow
19. Knowledge Check 5: Simulation Mismatch
20. Lab: Debug Simulation Mismatches
21. Assessment: Simulation Mismatch

12 Pattern Optimization 8 Topics

1. Standard ATPG Process
2. ATPG Pattern Compression
3. Knowledge Check 1: Pattern Optimization
4. Clock Domain Analysis
5. ATPG create _patterns Command
6. EDT Compression Overview
7. Knowledge Check 2: Pattern Optimization
8. Assessment: Pattern Optimization

13 Tessent Scan and ATPG Exam 1 Topic

1. Level 1 Exam - Tessent Scan and ATPG

Tessent IJTAG 10  Chapters

You will learn how to use the IEEE 1687 IJTAG standard with Tessent tools to accomplish your test tasks using a variety of test IP.

1 Introduction and Overview 6 Topics

1. IEEE 1687 Motivation
2. IEEE 1687 Solution
3. IEEE1149 / IEEE1500 / IEEE1687
4. Tessent Usage Model
5. Tessent IJTAG Overview
6. Assessment: Introduction and Overview

2 Instrument Connectivity Language​ ICL 17 Topics

1. ICL Overview
2. ICL Semantics
3. ICL Scan Registers
4. ICL Mux, Instances and Logic Signals
5. Knowledge Check 1: Instrument Connectivity Language​ ICL
6. ICL Building Blocks - TDR and SIB 
7. ICL Building Blocks – TAP
8. Advanced ICL – Parameter, Alias, and Enum
9. Knowledge Check 2: Instrument Connectivity Language​ ICL
10. ICL Versus Verilog Modeling
11. ICL Netlist
12. Creating ICL Modules
13. Reading ICL
14. DRC - ICL Syntax and Semantics
15. Knowledge Check 3: Instrument Connectivity Language​ ICL
16. Lab 2: Instrument Connectivity Language​ ICL
17. Assessment: Instrument Connectivity Language​ ICL

3 Procedural Description Language PDL 15 Topics

1. Procedural Description Language Overview
2. Basic PDL Commands – iNote, iRead, iWrite
3. PDL Commands - iApply 
4. Knowledge Check 1: Procedural Description Language PDL
5. PDL Commands - iCall, iProc
6. PDL Commands - iPrefix, iMerge, iTake, iRelease
7. PDL Commands - iReset
8. Knowledge Check 2: Procedural Description Language PDL
9. PDL Commands – Clocks
10. Reading PDL
11. Creating and Writing PDL Patterns 
12. Pattern Beginning and End
13. Knowledge Check 3: Procedural Description Language PDL
14. Lab 3: Procedural Description Language PDL
15. Assessment: Procedural Description Language PDL

4 Hardware and Timing 6 Topics

1. IJTAG Architecture
2. IJTAG Events
3. Simple Operating Example
4. Multi Instrument Example
5. Design Considerations
6. Assessment: Hardware and Timing

5 ICL Extraction 19 Topics

1. Overview
2. ICL Extraction Overview
3. ICL Extraction Flow
4. Module Matching
5. Clocks
6. Knowledge Check 1: ICL Extraction
7. Top-Down or Bottom-Up
8. Top-Down
9. Bottom-Up
10. Top-Down Bottom-Up Comparison
11. Knowledge Check 2: ICL Extraction
12. Writing ICL
13. ICL Extraction Attributes
14. Further Extraction Control
15. ICL Network Extraction DRC
16. DRC Debug
17. Knowledge Check 3: ICL Extraction
18. Lab 5: ICL Extraction
19. Assessment: ICL Extraction

6 PDL Retargeting 18 Topics

1. PDL Retargeting Principle
2. Retargeting through the SIB
3. PDL Retargeting Flow
4. Working with PDL Procedures
5. Creating a Retargeted Pattern
6. Knowledge Check 1: PDL Retargeting
7. PDL Retargeting with Aliases
8. Defining the Clocks
9. Pattern Timing
10. Knowledge Check 2: PDL Retargeting
11. Controlling the Reset
12. Controlling the Pattern End
13. Controlling the iApply, iMerge, iRead, iWrite
14. Retargeting Options
15. Pattern Annotations
16. Knowledge Check 3: PDL Retargeting
17. Lab 6: PDL Retargeting
18. Assessment: PDL Retargeting

7 ICL Network Insertion 17 Topics

1. Integrated Flow
2. Reading ICL
3. The DFT Specification
4. Using 3rd Party IP in the DFT Specification
5. Knowledge Check 1: ICL Network Insertion
6. Understanding the DFT Specification
7. Customizing the DFT Specification - Part 1
8. Customizing the DFT Specification - Part 2
9. IJTAG with the TSDB
10. Knowledge Check 2: ICL Network Insertion
11. DFT Signals
12. Controlling the IJTAG IP Insertion 
13. Two Pin Serial Port Basics
14. IJTAG Introspection
15. Knowledge Check 3: ICL Network Insertion
16. Lab 7: ICL Network Insertion
17. Assessment: ICL Network Insertion

8 Migrating Designs to IJTAG 8 Topics

1. Migrating Designs to IJTAG
2. Migrating IEEE 1149.1 – Part 1
3. Migrating IEEE 1149.1 - Part 2
4. Migrating IEEE 1500 Part 1
5. Migrating IEEE 1500 Part 2
6. Migrating Other Designs
7. Lab 8: Migrating Designs to IJTAG
8. Assessment: Migrating Designs to IJTAG

9 IJTAG in Tessent 9 Topics

1. Tessent IJTAG Architecture
2. STI and SRI
3. IJTAG in Tessent MBIST
4. Knowledge Check 1: IJTAG in Tessent
5. IJTAG with Tessent ATPG
6. IJTAG in Tessent SSN
7. Knowledge Check 2: IJTAG in Tessent
8. Lab 9: IJTAG in Tessent
9. Assessment: IJTAG in Tessent

10 Tessent IJTAG Exam 1 Topic

1. Level 1 Exam - Tessent IJTAG

Tessent MemoryBIST 9  Chapters

You will learn how to implement DFT for memory test through Tessent Shell tool environment & how to utilize it to implement MemoryBIST solutions for your design

1 Introduction to Tessent MemoryBIST 9 Topics

1. Tessent MemoryBIST Implementation
2. Tessent MemoryBIST Capabilities
3. Tessent MemoryBIST Algorithms
4. Knowledge Check 1: Introduction to MemoryBIST
5. Memory Library File Overview
6. The Hierarchical Bottom Up Implementation Flow
7. Tessent MemoryBIST Flow
8. Knowledge Check 2: Introduction to MemoryBIST
9. Assessment: Introduction to MemoryBIST

2 Standard MemoryBIST Flow 8 Topics

1. Loading the Design and Libraries
2. Setting the Requirements for DFT Implementation
3. Knowledge Check 1: Standard MemoryBIST Flow
4. DFT Specification Creation and Processing Overview
5. Perform ICL Network Extraction and Pattern Generation
6. Knowledge Check 2: Standard MemoryBIST Flow
7. Lab: Standard MemoryBIST Flow
8. Assessment: Standard MemoryBIST Flow

3 Clocks and Clock DRCs 9 Topics

1. Managing Clock Control Elements - Part 1
2. Managing Clock Control Elements - Part 2
3. Knowledge Check 1: Clocks and Clock DRC
4. MemoryBIST DFT Specifications
5. MemoryBIST Patterns Specifications
6. Performing Pre-DFT DRCs
7. Knowledge Check 2: Clocks and Clock DRC
8. Lab: Clocks and DRCs
9. Assessment: Clocks and Clock DRC

4 DefaultsSpecification and DFTSpecification 9 Topics

1. DefaultsSpecifications Overview
2. DefaultsSpecifications General Options
3. Knowledge Check 1: DefaultsSpecification and DFTSpecification
4. Memory BIST Options
5. Editing Specifications: Using the GUI
6. Editing Specifications: Using Command Line/Dofile
7. Knowledge Check 2: DefaultsSpecification and DFTSpecification
8. Lab: Specifications and Specification Editing
9. Assessment: DefaultsSpecification and DFTSpecification

5 MemoryBIST Hierarchical Top Level Flow 11 Topics

1. Top Level Flow Differences
2. Bonding Configurations
3. Tessent MBIST Top Level Flow: Loading the Design
4. Tessent MBIST Flow: Generating DFT Specification
5. Knowledge Check 1: MemoryBIST Hierarchical Top Level Flow
6. Tessent MBIST Top Level Flow: Extracting ICL Network
7. Tessent MBIST Top Level Flow: Creating and Processing Patterns Specification
8. Tessent MBIST Top Level Flow: Manufacturing Patterns
9. Knowledge Check 2: MemoryBIST Hierarchical Top Level Flow
10. Lab: Top/Chip Level, Boundary Scan
11. Assessment: MemoryBIST Hierarchical Top Level Flow

6 MemoryBIST Debug Patterns 8 Topics

1. Creating Debug and Characterization Patterns
2. Testing Single Test Step and Single Memory
3. Knowledge Check 1: MemoryBIST Debug Patterns
4. More Pattern Generation Options
5. Tessent MemoryBIST Diagnosis
6. Knowledge Check 2: MemoryBIST Debug Patterns
7. Lab: MemoryBIST Debug Patterns
8. Assessment: MemoryBIST Debug Patterns

7 Built-in Self Repair 9 Topics

1. Tessent MemoryBIST: Self-Repair Architecture
2. Tessent MemoryBIST: Built-In Repair Strategies
3. Tessent MemoryBIST: Manufacturing Repair Flow
4. Knowledge Check 1: Built-in Self Repair
5. Tessent MemoryBIST: Repair Flow
6. More on Fuse Boxes
7. Knowledge Check 2: Built-in Self Repair
8. Lab: Tessent MemoryBIST - Built-in Self Repair
9. Assessment: Built-in Self Repair

8 Additional Topics 3 Topics

1. Design Synthesis Considerations
2. Tessent SiliconInsight Overview
3. Assessment: Additional Topics

9 Tessent MemoryBIST Exam 1 Topic

1. Level 1 Certification - Tessent MemoryBIST

Tessent TestKompress 7  Chapters

You will be introduced to Embedded Deterministic Test (EDT) technology, and you will learn how to create compressed test patterns and how to debug EDT DRCs.

1 TestKompress Basics 15 Topics

1. Introduction to Tessent TestKompress
2. Standard Test vs. TestKompress Test Comparison - Part1
3. Standard Test vs. TestKompress Test Comparison - Part2
4. Knowledge Check 1: TestKompress Basics
5. Tessent TestKompress Logic Placement
6. Tessent TestKompress Control Signals
7. The Decompressor
8. The Compactor
9. Scan Chain Masking and Fault Aliasing
10. Knowledge Check 2: TestKompress Basics
11. Reporting EDT Logic Configurations
12. Bypass Logic and Lockup Cells
13. Pipeline Stages
14. Knowledge Check 3: TestKompress Basics
15. Assessment: TestKompress Basics

2 TestKompress Insertion Flows 18 Topics

1. Tessent TestKompress Commands
2. Logic Creation Flows Overview
3. Knowledge Check 1: TestKompress Insertion Flows
4. Post-Synthesis External Logic Flow: Scan Insertion and EDT Creation
5. Post-Synthesis External Logic Flow: The Synthesis and Pattern Generation
6. Knowledge Check 2: TestKompress Insertion Flows
7. Lab: TestKompress Insertion Flows - Post-Synthesis External Logic Creation
8. Post-Synthesis Internal Logic Creation Flow
9. Post-Synthesis Internal Logic Flow: Scan Insertion and EDT Creation
10. Post-Synthesis Internal Logic Flow: The Synthesis and Pattern Generation
11. Knowledge Check 3: TestKompress Insertion Flows
12. Lab: TestKompress Insertion Flows - Post-Synthesis Internal Logic Creation
13. Pre-Synthesis Logic Flow
14. Compressed Test Patterns Generation
15. EDT Pattern Reordering
16. Knowledge Check 4: TestKompress Insertion Flows
17. Lab: TestKompress Insertion Flows - Pre-synthesis EDT logic creation
18. Assessment: TestKompress Insertion Flows

3 TestKompress Design Rule Checking 16 Topics

1. K19 Design Rule Check
2. Debugging K19 DRC Using Gate Reporting
3. K20 Design Rule Check
4. K22 Design Rule Checks
5. Possible DRC Error Causes
6. Knowledge Check 1: TestKompress DRC
7. The EDT Finder
8. The EDT Finder DRCs
9. Reporting EDT Logic Using EDT Finder
10. Knowledge Check 2: TestKompress DRC
11. Lab 1: TestKompress DRC Simulation
12. Pattern Simulation and Automatic Mismatch Debugging
13. Simulation Mismatch Debugging
14. Knowledge Check 3: TestKompress DRC
15. Lab 2: TestKompress DRC Simulation
16. Assessment: TestKompress DRC

4 Tessent TestKompress Performance Optimization 11 Topics

1. TestKompress Performance Maximization and Evaluation
2. Compression Analysis
3. Compression Analysis Procedure and Results
4. Automating Compression Analysis and Resolving Issues
5. Knowledge Check 1: Tessent TestKompress Performance Optimization
6. Test Points
7. Inserting Test Points
8. Pre-Scan Test Point Insertion Flow
9. Knowledge Check 2: Tessent TestKompress Performance Optimization
10. Lab: Tessent TestKompress Performance Optimization
11. Assessment: Tessent TestKompress Performance Optimization

5 Modular & Hierarchical TestKompress 16 Topics

1. Modular Tessent TestKompress Implementation
2. Module Level Core Mapping Flow
3. Top Level Core Mapping Flow
4. Knowledge Check 1: Modular & Hierarchical TestKompress
5. Broadcasting to Identical Blocks Implementation
6. Modular TestKompress with Channel Sharing
7. Channel Sharing Implementation
8. Knowledge Check 2: Modular & Hierarchical TestKompress
9. Top Level Flat ATPG vs. Hierarchical ATPG
10. Hierarchical DFT Flow Overview
11. Pattern Retargeting
12. Grayboxes Overview
13. Streaming Scan Network Overview
14. Knowledge Check 3: Modular & Hierarchical TestKompress
15. Lab: Modular & Hierarchical TestKompress
16. Assessment: Modular & Hierarchical TestKompress

6 Advanced Topics 15 Topics

1. Chain Masking Options and Dual Configurations
2. Low Power ATPG
3. Knowledge Check 1: Advanced Topics
4. Low Power ATPG Usage - Part1
5. Low Power ATPG Usage - Part2
6. Reporting Power Metrics
7. Managing Low Power Patterns
8. Knowledge Check 2: Advanced Topics
9. Power-Aware Test Flow - Part 1
10. Power-Aware Test Flow - Part 2
11. Low Pin Count Test
12. Tessent On-Chip Clock Controller
13. Tessent SiliconInsight Motivation
14. Knowledge Check 3: Advanced Topics
15. Assessment: Advanced Topics

7 Tessent TestKompress Exam 1 Topic

1. Level 1 Certification - Tessent TestKompress

Tessent Integrated Flow 8  Chapters

Learn how to implement MBIST, Boundary Scan, IJTAG, Scan Insertion, and TestKompress into your design to obtain high test quality using multiple Tessent tools.

1 Tessent Shell Overview 13 Topics

1. Getting Started with Tessent Shell
2. Understanding Contexts and System Modes
3. Knowledge Check 1: Tessent Shell Overview
4. Design Objects, Attributes, and Data Models
5. Creating and Using Collections
6. Design Editing
7. Knowledge Check 2: Tessent Shell Overview
8. Design Introspection
9. Design Tracing
10. Understanding Configuration Specifications
11. Knowledge Check 3: Tessent Shell Overview
12. Virtual Lab: Tessent Shell Overview
13. Assessment: Tessent Shell Overview

2 IJTAG Introduction 13 Topics

1. Understanding the IEEE 1687 Objectives
2. Contrasting IJTAG with IEEE 1149.1 and 1500
3. Connecting IJTAG to IEEE 1149.1 and 1500
4. Knowledge Check 1: IJTAG Introduction
5. Using ICL and PDL files
6. Virtual Lab 1: IJTAG Introduction
7. Retargeting PDL in the Design
8. Basic Timing and Clock Definition
9. ICL Network Extraction
10. Knowledge Check 2: IJTAG Introduction
11. Understanding the STI and SRI Differences
12. Virtual Lab 2: IJTAG Introduction
13. Assessment: IJTAG Introduction

3 Basic Block-based Bottom-up DFT Flow Overview 13 Topics

1. Introduction to Basic Flow Used for all Design Levels
2. Design Context, Design Id, and Loading Designs
3. Specifying Design Level and TSDB Output Directory
4. Creating and Processing DFT Specifications
5. Knowledge Check 1: Basic Block-based Bottom-up DFT Flow Overview
6. Viewing, Editing, and Customizing DFT Specifications
7. Using the DefaultsSpecifications
8. Using the Tessent Shell Database (TSDB)
9. Knowledge Check 2: Basic Block-based Bottom-up DFT Flow Overview
10. PatternsSpecification and Test Bench Simulation
11. Virtual Lab: Basic Block-based Bottom-up DFT Flow Overview
12. Understanding Top-level Differences
13. Assessment: Basic Block-based Bottom-up DFT Flow Overview

4 MBIST creation overview 15 Topics

1. Loading the Design and Libraries
2. Loading the Design and Libraries; Examples and Additional Commands
3. Setting the Requirements for DFT Implementation
4. DFT Specification Creation and Loading Overview
5. Editing and Processing the DFT Specification
6. Knowledge Check 1: MBIST Creation Overview
7. Perform ICL network extraction
8. Creating and Processing the PatternsSpecificaton
9. Simulating Patterns for Validation
10. Virtual lab : MBIST Creation Overview
11. Clocks Overview
12. Knowledge Check 2: MBIST Creation Overview
13. MBIST differences at the chip-level
14. Understand Auxiliary Bscan for TAM, InputOutputPorts
15. Assessment : MBIST Creation Overview

5 Logic Test Creation 12 Topics

1. Introduction to Logic Test
2. Understanding DFT signals
3. On-chip Clock Controller (OCC) Insertion
4. Pre-DFT DRCs and Common Debugging
5. Creating and Customizing a specification for Logic Test
6. Knowledge Check 1: Logic Test Creation
7. Modal Connections
8. Synthesis Optimization Requirements
9. Knowledge Check 2: Logic Test Creation
10. Pattern Specification and Simulation
11. Virtual Lab: Logic Test Creation
12. Assessment: Logic Test Creation

6 Scan Insertion 9 Topics

1. Multi-mode Scan Insertion
2. Multi-mode Scan Insertion: Command Examples
3. Hierarchical DFT Overview
4. Knowledge Check 1: Scan Insertion
5. Hierarchical Scan Insertion
6. Virtual Lab: Scan Insertion
7. Introduction to VersaPoints Test Points
8. Knowledge Check 2: Scan Insertion
9. Assessment: Scan Insertion

7 Test Pattern Generation 15 Topics

1. Overview of Automatic Test Pattern Generation (ATPG)
2. Flat ATPG
3. Knowledge Check 1: Test Pattern Generation
4. Saving ATPG Results
5. Compiling and Simulating Verilog Patterns
6. Virtual Lab 1: Test Pattern Generation
7. Knowledge Check 2: Test Pattern Generation
8. Transition ATPG Patterns
9. Virtual Lab 2: Test Pattern Generation
10. Knowledge Check 3: Test Pattern Generation
11. Hierarchical ATPG
12. Pattern Retargetting
13. Virtual Lab 3: Test Pattern Generation
14. Knowledge Check 4: Test Pattern Generation
15. Assessment: Test Pattern Generation

8 Tessent Integrated Flow Exam 1 Topic

1. Level 1 Exam - Tessent Integrated Flow

Tessent SiliconInsight 4  Chapters

You will learn how to use Tessent SiliconInsight, understand the MBIST offline diagnosis flow, as well as ATPG offline diagnosis flow in non-TSDB.

1 Tessent SiliconInsight Introduction 4 Topics

1. Tessent SiliconInsight Introduction - Use cases in various debug phases
2. Common Knowledge about Setup- Setup Files & Do-file
3. Common Knowledge about Setup - GUI
4. Assessment: Tessent SiliconInsight Introduction

2 SiliconInsight Desktop 4 Topics

1. Hardware Environment
2. Setup Verification
3. Lab 1: SiliconInsight Desktop
4. Assessment: SiliconInsight Desktop

3 MBIST Offline Diagnosis Flow 8 Topics

1. ESOE Offline Diagnosis Flow - Overview
2. ATE Offline MBIST Diagnosis - ESOE CDP Generation
3. Knowledge Check 1: MBIST Offline Diagnosis Flow
4. ATE Offline MBIST Diagnosis - ATE Test Program
5. ATE Offline MBIST Diagnosis - Post-Test Offline-Processing
6. Knowledge Check 2: MBIST Offline Diagnosis Flow
7. Lab 2: MBIST Offline Diagnosis Flow
8. Assessment: MBIST Offline Diagnosis Flow

4 ATPG Offline Diagnosis Flow (Non-TSDB Flow) 5 Topics

1. ATPG / EDT Diagnosis - Overview
2. Preparations for SiliconInsight ATPG
3. SiliconInsight ATPG - Debug & Diagnosis Operations
4. Lab 3: ATPG Offline Diagnosis Flow (Non-TSDB Flow)
5. Assessment: ATPG Offline Diagnosis Flow (Non-TSDB Flow)

Tessent Hybrid TK/LBIST 4  Chapters

You will learn how to use Tessent TestKompress and LogicBIST together to add both types of logic in your IC to get the benefits of both solutions.

1 Hybrid TK/LBIST Introduction 8 Topics

1. Hybrid TK/LBIST Overview
2. Hybrid TK/LBIST Shared Logic
3. Hybrid TK/LBIST Embedded Structures
4. Knowledge Check 1: Hybrid TK/LBIST Introduction
5. Hybrid TK/LBIST Clocking
6. Shift-Low Power Controller and Encoding Logic
7. Knowledge Check 2: Hybrid TK/LBIST Introduction
8. Assessment: Hybrid TK/LBIST Introduction

2 Hybrid TK/LBIST Features 13 Topics

1. Hybrid TK/LBIST Capabilities and Limitations
2. Hybrid TK/LBIST Test Modes
3. Knowledge Check 1: Hybrid TK/LBIST Features
4. Test Point Insertion - Part 1
5. Test Point Insertion - Part 2
6. Hybrid TK/LBIST X-Bounding
7. Knowledge Check 2: Hybrid TK/LBIST Features
8. Lab: Test Point Insertion and X-Bounding
9. Warm-up Patterns and Burn-In Test Mode
10. Configurable Dead Cycles
11. Hybrid TK/LBIST Diagnosis
12. Knowledge Check 3: Hybrid TK/LBIST Features
13. Assessment: Hybrid TK/LBIST Features

3 Hybrid TK/LBIST Implementation and Pattern Generation 12 Topics

1. Hybrid TK/LBIST Insertion Flow Overview
2. Hybrid TK/LBIST Implementation Flow
3. Hybrid TK/LBIST Operation Steps
4. Knowledge Check 1: Hybrid TK/LBIST Implementation and Pattern Generation
5. Hybrid TK/LBIST Design Preparation
6. Hybrid TK/LBIST IP Insertion Example
7. Knowledge Check 2: Hybrid TK/LBIST Implementation and Pattern Generation
8. Hybrid TK/LBIST Fault Simulation
9. Hybrid TK/LBIST Pattern Generation
10. Knowledge Check 3: Hybrid TK/LBIST Hybrid TK/LBIST Implementation and Pattern Generation
11. Lab: Hybrid TK/LBIST Hybrid TK/LBIST Implementation and Pattern Generation
12. Assessment: Hybrid TK/LBIST Hybrid TK/LBIST Implementation and Pattern Generation

4 Independent Hybrid TK/LBIST Insertion Flow 6 Topics

1. Hybrid TK/LBIST Independent Insertion Motivations
2. EDT and LogicBIST IP Generation for Independent Insertion Flow - Part 1
3. EDT and LogicBIST IP Generation for Independent Insertion Flow - Part 2
4. Integrating SSN with Independent Insertion
5. Conurrent Flow Vs. Independent Insertion Flow
6. Assessment: Independent Hybrid TK/LBIST Insertion Flow

Tessent Diagnosis 11  Chapters

This learning path focuses on Tessent Diagnosis within the Diagnosis Driven Yield Analysis (DDYA) flow.

1 Introduction 12 Topics

1. Tessent Diagnosis and Diagnosis Driven Yield Analysis
2. Tessent Diagnosis Process
3. Knowledge Check 1: Introduction
4. ATPG Fault Models, Patterns, and Defect Detection
5. Knowledge Check 2: Introduction
6. Tesssent Diagnosis Flow
7. Flat vs Hierarchical ATPG and Diagnosis
8. Tessent Diagnosis Supports Yield Enhancement Analysis Methodologies
9. Knowledge Check 3: Introduction
10. Tool Help and Documentation
11. Lab1: Introduction
12. Assessment: Introduction

2 Preparing for Diagnosis 8 Topics

1. Archiving ATPG Patterns and Flat Models for Diagnosis
2. Importance of ATPG Patterns and Flat Model Consistency
3. Knowledge Check 1: Preparing for Diagnosis
4. Validating and Debugging ATPG Patterns to Flat Models
5. Debug Failure File Consistency Issues
6. Knowledge Check 2: Preparing for Diagnosis
7. Lab2: Preparing for Diagnosis
8. Assessment: Preparing for Diagnosis

3 Failure Files 10 Topics

1. Understanding Data requirements for Diagnosis
2. Specification and Usage of Tracking Information
3. Knowledge Check 1: Failure Files
4. Truncated Failure Files and the Failure Buffer Limit Reached Keyword
5. Knowledge Check 2: Failure Files
6. Cycle Based Failure File and Datalogging for Diagnosis
7. Converting Tester Datalog to Tessent Failure File Format
8. Knowledge Check 3: Failure Files
9. Lab3: Failure Files
10. Assessment: Failure Files

4 Layout Database 7 Topics

1. Layout-Aware Diagnosis Defined
2. Creating a Layout Database
3. knowledge Check 1: Layout Database
4. Layout Database Creation Debug
5. Knowledge Check 2: Layout Database
6. Lab4: Layout Database
7. Assessment: Layout Database

5 Diagnosis Modes and Output 12 Topics

1. Tessent ATPG, Diagnosis Process, and Layout usage
2. Symptoms, Suspect Classifications, and Observed Behaviors
3. Knowledge Check 1: Diagnosis Modes and Output
4. Chain Diagnosis
5. Scan (Logic) Diagnosis
6. Knowledge Check 2: Diagnosis Modes and Output
7. Running Tessent Diagnosis
8. Reading Tessent Diagnosis Reports
9. Graphically Viewing Diagnosis Reports, Generating encoded reports, and Diagnosis Options
10. Knowledge Check 3: Diagnosis Modes and Output
11. Lab5: Diagnosis Modes and Output
12. Assessment: Diagnosis Modes and Output

6 Diagnosing Hierarchical Designs 8 Topics

1. Hierarchical Diagnosis Concepts
2. Pattern Retargeting Concepts and Requirements
3. Knowledge Check 1: Diagnosing Hierarchical Designs
4. Reverse Map Tessent Formated Failure Files and Validating Reverse Map Flow
5. Creating Core LDBs for, and Running, Hierarchical Diagnosis
6. Knowledge Check 2: Diagnosing Hierarchical Designs
7. Lab6: Diagnosing Hierarchical Designs
8. Assessment: Diagnosing Hierarchical Designs

7 Diagnosis Driven Yield Analysis 8 Topics

1. Methodology and Tool Flow
2. Setting up and Running Tessent Diagnosis Server
3. Knowledge Check 1: Diagnosis Driven Yield Analysis
4. Setting up and Running Tessent Diagnosis Server in Dynamic Partitioning Mode
5. Introduction to Tessent YieldInsight
6. Knowledge Check 2: Diagnosis Driven Yield Analysis
7. Lab7: Diagnosis Driven Yield Analysis
8. Assessment: Diagnosis Driven Yield Analysis

8 Cell-Aware Diagnosis 5 Topics

1. Cell-Aware Diagnosis Overview
2. Cell-Fault Library, Running Cell-Aware Diagnosis and Report Content
3. Knowledge Check 1: Cell-Aware Diagnosis
4. Lab8: Cell-Aware Diagnosis
5. Assessment: Cell-Aware Diagnosis

9 Advanced Topics 12 Topics

1. Configuring Tessent Diagnosis
2. Failing Scan Cell Identification
3. Knowledge Check 1: Advanced Topics
4. Diagnosing Frequency Dependent Defects (gross_delay)
5. Identifying Slow Paths (at_speed)
6. Knowledge Check 2: Advanced Topics
7. Diagnosing IDDQ Failures
8. Improving Diagnosis: Iterative Diagnosis
9. Adding/Updating DFM and RCD Data in Existing Diagnosis Reports
10. Knowledge Check 3: Advanced Topics
11. Lab9: Advanced Topics
12. Assessments: Advanced Topics

10 SSN Diagnosis Process 13 Topics

1. SSN Introduction
2. SSN Overview
3. SSN Diagnosis Overview
4. KC1
5. SSN Handling Identical Cores; With or Without On-chip Compare
6. SSN Test Program Requirements
7. SSN Patterns and Retesting
8. KC2
9. SSN Writing the Pattern Files
10. SSN Failure Data Collection and the ATPG-ATE Environment
11. KC3
12. Lab10: SSN Diagnosis Process
13. Assessment

11 Tessent Diagnosis Exam 1 Topic

1. Level 1 Certification - Tessent Diagnosis

Tessent Streaming Scan Network (SSN) 7  Chapters

Learn how to leverage the Tessent Shell environment to insert SSN and other test logic into SoCs, generating & verifying test patterns for manufacturing test.

1 SSN Technology Introduction 14 Topics

1. Motivation to Use SSN
2. SSN Architecture Overview
3. Streaming Scan Host (SSH)
4. Scan Data Streaming Packets
5. Knowledge Check 1: SSN Technology Introduction
6. Using Standard OCC with SSN
7. Motivation for Bandwidth Tuning with SSN
8. Verifying SSN Components - Part 1
9. Verifying SSN Components - Part 2
10. Understanding SSH Timing
11. SSN DRC
12. Knowledge Check 2: SSN Technology Introduction
13. Lab: SSN Introduction
14. Assessment SSN Technology Introduction

2 SSN Block Level Work Flow 14 Topics

1. Block-Level Flow with SSN
2. SSN Block-Level Flow: First DFT Insertion Pass
3. SSN Block-Level Flow: Second DFT Insertion Pass
4. Knowledge Check 1: SSN Work Flow - Block-Level Flow
5. SSN Block-Level Flow: Synthesis Option and Scan Chain Insertion
6. SSN Block-Level Flow: ICL Based Patterns Verification
7. SSN Block-Level Flow: Generating ATPG Patterns
8. Knowledge Check 2: SSN Work Flow - Block-Level Flow
9. SSN Block-Level Pattern Verification Summary
10. Test Bench Parameters with SSN
11. SSN Implementation Commands
12. Knowledge Check 3: SSN Work Flow - Block-Level Flow
13. Lab: Block-level SSN Insertion
14. Assessment: SSN Work Flow - Block Level Flow

3 SSN Datapath Planning 5 Topics

1. Introduction to SSN Datapath Planning
2. Implementing the SSN Datapath using Commands
3. Implementing the SSN Datapath using GUI
4. Lab: SSN Datapath Planning
5. Assessment SSN Datapath Planning

4 SSN Top Level Work Flow 11 Topics

1. Top-Level Flow with SSN
2. SSN Top-Level Flow: First DFT Insertion Pass
3. SSN Top-Level Flow: Second DFT Insertion Pass
4. Knowledge Check 1: SSN Work Flow - Top Level Flow
5. SSN Top-Level FLow: Synthesis and Scan Insertion
6. SSN Top-Level Flow: Test Patterns Generation
7. SSN Top-Level Flow: Pattern Retargeting
8. SSN Top-Level Pattern Verification Summary
9. Knowledge Check 2: SSN Work Flow - Top Level Flow
10. Lab: Top-level SSN Insertion
11. Assessment: SSN Work Flow - Top Level Flow

5 SSN Clocking and Diagnosis 5 Topics

1. Clock Tree Types
2. Managing Timing of SSN Datapath-Part1
3. Managing Timing of SSN Datapath-Part2
4. Failure Mapping of SSN Pattern Failures
5. Assessment: SSN Clocking and Diagnosis

6 SSN Advanced Topics 7 Topics

1. Advanced Topics
2. On-Chip Compare Logic Introduction
3. On-Chip Compare Logic: Diagnosis
4. LVX (LVI/LVP) Support with SSN
5. Burn-In Patterns with SSN
6. Lab: SSN Advanced Topics
7. Assessment: SSN Advanced Topics

7 Tessent Streaming Scan Network Exam 1 Topic

1. Level 1 Exam - Tessent Streaming Scan Network

Tessent Shell Automation 6  Chapters

You will learn how to use your Tcl knowledge to perform database introspection for reporting and for design editing for testability improvements.

1 Tessent Shell Basics 18 Topics

1. What is Tessent Shell?
2. Contexts and System Modes - Part 1
3. Contexts and System Modes - Part 2
4. TCL Commands and Help
5. Knowledge Check 1: Tessent Shell Basics
6. Design Data and Object Types
7. Pre-Defined Attributes and Data Models
8. Hierarchical Data Model
9. Instances and Pins
10. Nets and Pseudo Ports
11. Knowledge Check 2: Tessent Shell Basics
12. Flat Model and Gate Pins
13. ICL Data Model, Current Design and Level
14. User-Defined Attributes
15. Tessent Visualizer
16. Knowledge Check 3: Tessent Shell Basics
17. Lab 1: Exploring the Help System
18. Assessment: Tessent Shell Basics

2 Basic TCL Review 8 Topics

1. Variables, Grouping, and Substitution
2. Scopes and Data Types
3. If, While, and For Commands
4. Knowledge Check 1: Basic TCL Review
5. Regular Expression, I/O, and Procedure
6. Knowledge Check 2: Basic TCL Review
7. Lab 2: Working with Files, Replacing Modules
8. Assessment: Basic TCL Review

3 Design Introspection and Editing 11 Topics

1. Tessent Collections
2. Design Introspection
3. Design Editing - Part 1
4. Design Editing - Part 2
5. Knowledge Check 1: Design Introspection and Editing
6. Fan-ins and Fan-outs
7. Trace Flat Model
8. Knowledge Check 2: Design Introspection and Editing
9. Tracing Examples
10. Lab 3: Replacing Modules and Creating New Connections
11. Assessment: Design Introspection and Editing

4 Creating and Using Scripts 9 Topics

1. Tool Flow and Transcripts
2. Transcript Options
3. Knowledge Check 1: Creating and Using Scripts
4. Source and Dofile
5. Scripts and Procedures
6. Command Creation
7. Knowledge Check 2: Creating and Using Scripts
8. Lab 4: Create a Procedure to Replace Cells
9. Assessment: Creating and Using Scripts

5 Advanced Topics 6 Topics

1. Environment Variables and TCL Packages
2. Knowledge Check 1: Advanced Topics
3. IJTAG Introduction
4. Configuration Specification
5. Knowledge Check 2: Advanced Topics
6. Assessment: Advanced Topics

6 Tessent Shell Automation Exam 1 Topic

1. Level 1 Exam - Tessent Shell Automation

Tessent YieldInsight 8  Chapters

This course covers the DDYA process, including is an overview of Tessent Diagnosis and how to use Tessent YieldInsight to identify the true yield limiters.

1 Introduction to DDYA 8 Topics

1. Diagnosis-Driven Yield Analysis Introduction
2. Causes of Yield Loss
3. Knowlege check 1: Introduction to DDYA
4. Diagnosis-Driven Yield Analysis Benefits
5. Statistics Refresh
6. Knowlege check 2: Introduction to DDYA
7. Lab: Introduction to DDYA
8. Assessment

2 Scan and Diagnosis Basics 10 Topics

1. Scan Test and its Benefits
2. Tessent Diagnosis Functionality and Purpose
3. Tessent Diagnosis Basics
4. Knowledge Check 1: Scan and Diagnosis Basics
5. Tessent Diagnosis Concepts
6. Tessent Diagnosis Flows
7. Diagnosis Results and Tessent YieldInsight
8. Knowledge Check 2: Scan and Diagnosis Basics
9. Lab: Scan and Diagnosis Basics
10. Assessment

3 Tessent YieldInsight Fundamentals 10 Topics

1. Preparing for an Analysis
2. Preparing for Tessent YieldInsight Analysis Demonstration
3. Genres, Types of Analysis, and Signatures
4. Knowledge Check 1: Tessent YieldInsight Fundamentals
5. Running a Signature Analysis and Results Visualizations - Part1
6. Running a Signature Analysis and Results Visualizations - Part2
7. Analysis and Visualizations Demonstration
8. Knowledge Check 2: Tessent YieldInsight Fundamentals
9. Lab: Tessent YieldInsight Fundamentals
10. Assessment

4 Yield Analysis: Evolved 12 Topics

1. Defect Landscape
2. Potential Yield Improvement
3. Knowledge Check 1: Yield Analysis: Evolved
4. Tessent Yield Insight Concepts - Par1
5. Tessent Yield Insight Concepts-Part2
6. Tessent YieldInsight Usage Model Demonstration
7. Knowledge Check 2: Yield Analysis: Evolved
8. Driving Tessent YieldInsight
9. Demo-Driving Tessent YieldInsight
10. Knowledge Check 3: Yield Analysis: Evolved
11. Lab: Yield Analysis: Evolved
12. Assessment

5 Assessing Diagnosis Data and Creating Populations 9 Topics

1. Guiding Principles
2. Assessing the Resolution and Merit of Diagnosis Data
3. Poor Quality Diagnosis Data Corrective Actions
4. Knowledge Check 1: Assessing Diagnosis Data and Creating Populatoins
5. Systematic Location Analysis
6. Assessing Diagnosi Data - Demonstration
7. Knowledge Check 2: Assessing Diagnosis Data and Creating Populatoins
8. Lab: Assessing Diagnosis Data and Creating Populatoins
9. Assessment

6 Analysis Scenarios 10 Topics

1. Chain Diagnosis Analysis
2. Chain Analysis Die Selection Demonstration
3. Knowledge Check 1: Analysis Scenarios
4. Analyzing Random Location Defects - Part1
5. Analyzing Random Location Defects - Part2
6. Trouble Shooting Example Scenatios
7. Knowledge Check 2: Analysis Scenarios
8. Driving Tessent YieldInsight: RCD Demonstration
9. Lab: Analysis Scenarios
10. Assessment

7 Advanced Topics 9 Topics

1. Export Table Data
2. Scripted Environments
3. Knowledge Check 1: Advanced Topics
4. Custom Signatures
5. Statistical Diagnosis
6. Design for Manufacturability
7. Knowledge Check 2: Advanced Topics
8. Lab: Advanced Topics
9. Assessment

8 Tessent YieldInsight Exam 1 Topic

1. Level 1 Exam Tessent YieldInsight

Tessent Multi-Die 7  Chapters

In this learning path, you will learn about the structure, main concepts, and implementation of Multi-Die devices, as well as their testing and diagnosis.

1 Multi-Die Overview 5 Topics

1. Multi-Die Motivations and Challenges
2. Introduction to Multi-Die Devices
3. Relevant IEEE Standards
4. DFT and Design Considerations for Multi-Die Devices
5. Assessment: Multi-Die Overview

2 Main Concepts for 2.5D Devices 9 Topics

1. 2.5D Devices
2. IEEE 1149.1 Compliance (tdi_local)
3. IEEE 1149.1 Compliance (tdo_daisy)
4. Knowledge Check 1: Main Concepts for 2.5D Devices
5. Boundary Scan Requirements and BSDL Extraction
6. Bonding Configurations
7. Clocking in Internal and External Scan Modes
8. Knowledge Check 2: Main Concepts for 2.5D Devices
9. Assessment: Main Concepts for 2.5D Devices

3 Multi-Die Flow for 2.5D Devices 13 Topics

1. Multi-Die Flow Outline for 2.5D Devices
2. Die-Level DFT Insertion at RTL-Level: First DFT Insertion Pass
3. Die-Level DFT Insertion at RTL-Level: Second DFT Insertion Pass
4. Knowledge Check 1: Multi-Die Flow for 2.5D Devices
5. Lab 1: 2.5D Device’s Full Flow (Exercises 1-2)
6. Die-Level DFT and Scan Insertion at Gate-Level
7. Knowledge Check 2: Multi-Die Flow for 2.5D Devices
8. Lab 1: 2.5D Device’s Full Flow (Exercises 3-5)
9. Package-Level Integration and Verification (Part 1)
10. Package-Level Integration and Verification (Part 2)
11. Knowledge Check 3: Multi-Die Flow for 2.5D Devices
12. Lab 1: 2.5D Device’s Full Flow (Exercises 6-9)
13. Assessment: Multi-Die Flow for 2.5D Devices

4 Main Concepts for 3D Devices 9 Topics

1. 3D Devices
2. Serial Test Access (PTAP/STAP)
3. Flexible Parallel Port
4. Knowledge Check 1: Main Concepts for 3D Devices
5. Die Wrapper Register
6. Scan Modes in 3D Devices
7. Clocking in Different Scan Modes
8. Knowledge Check 2: Main Concepts for 3D Devices
9. Assessment: Main Concepts for 3D Devices

5 Multi-Die Flow for 3D Devices 14 Topics

1. Multi-Die Flow Outline for 3D Devices
2. Core-Level DFT Insertion at RTL-Level
3. Core-Level DFT and Scan Insertion at Gate-Level
4. Knowledge Check 1: Multi-Die Flow for 3D Devices
5. Lab 2: 3D Device’s Full Flow (Exercises 1-3)
6. Die-Level DFT Insertion at RTL-Level
7. Die-Level DFT and Scan Insertion at Gate-Level
8. Knowledge Check 2: Multi-Die Flow for 3D Devices
9. Lab 2: 3D Device’s Full Flow (Exercises 4-6)
10. Stack-Level Integration and Verification (Part 1)
11. Stack-Level Integration and Verification (Part 2)
12. Knowledge Check 3: Multi-Die Flow for 2.5D Devices
13. Lab 2: 3D Device’s Full Flow (Exercises 7-8)
14. Assessment: Multi-Die Flow for 2.5D Devices

6 Testing and Diagnosis of Multi-Die Devices 6 Topics

1. Known-Good-Die (KGD) Wafer Probe Test
2. Sacrificial Pads: Muxed Probe Pads
3. Probe Pads Insertion in the DFT Flow
4. Diagnosis of Multi-Die Devices
5. Lab 3: Testing and Diagnosis
6. Assessment: Testing and Diagnosis of Multi-Die Devices

7 Tessent Multi-Die Exam 1 Topic

1. Level 1 Exam - Tessent Multi-Die

Tessent Scan and ATPG Exam 1  Chapter

Demonstrate your skills and knowledge in Tessent Scan and ATPG and earn a verifiable badge.

1 Tessent Scan and ATPG Exam 1 Topic

1. Level 1 Exam - Tessent Scan and ATPG

Tessent IJTAG Exam 1  Chapter

Earners of this badge have successfully completed the 50-question exam to show basic knowledge of the use of the IEEE 1687 IJTAG standard with Tessent tools.

1 Tessent IJTAG Exam 1 Topic

1. Level 1 Exam - Tessent IJTAG

Tessent MemoryBIST Exam 1  Chapter

Earners of this badge have successfully completed the 50 question exam to show basic knowledge of memory testing using Tessent MemoryBIST.

1 Tessent MemoryBIST Exam 1 Topic

1. Level 1 Certification - Tessent MemoryBIST

Tessent TestKompress Exam 1  Chapter

Complete the 50 questions exam to show basic knowledge of implementing EDT logic into your designs and creating compressed patterns using Tessent TestKompress.

1 Tessent TestKompress Exam 1 Topic

1. Level 1 Certification - Tessent TestKompress

Tessent Integrated Flow Exam 1  Chapter

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1. Level 1 Exam - Tessent Integrated Flow

Tessent SiliconInsight Exam 1  Chapter

Demonstrate your skills and knowledge in Tessent SiliconInsight, MBIST offline diagnosis flow, and ATPG offline diagnosis flow in non-TSDB.

1 Tessent SiliconInsight Exam 1 Topic

1. Level 1 Certification Exam - Tessent SiliconInsight

Tessent Hybrid TK/LBIST Exam 1  Chapter

Demonstrate your skills and knowledge in Tessent Hybrid TK/LBIST and earn a verifiable badge.

1 Tessent Hybrid TK/LBIST Exam 1 Topic

1. Level 1 Certification Exam - Tessent Hybrid TK/LBIST

Tessent Diagnosis Exam 1  Chapter

Demonstrate your skills and knowledge in Tessent Diagnosis and earn a verifiable badge.

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1. Level 1 Certification - Tessent Diagnosis

Tessent Streaming Scan Network Exam 1  Chapter

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1. Level 1 Exam - Tessent Streaming Scan Network

Tessent Shell Automation Exam 1  Chapter

Demonstrate your skills and knowledge in Tessent Shell environment and your Tcl knowledge in performing database introspection for reporting and design editing.

1 Tessent Shell Automation Exam 1 Topic

1. Level 1 Exam - Tessent Shell Automation

Tessent YieldInsight Exam 1  Chapter

Demonstrate your skills and knowledge in analyzing Tessent Diagnosis reports using Tessent YieldInsight and earn verifiable badge.

1 Tessent YieldInsight Exam 1 Topic

1. Level 1 Exam Tessent YieldInsight

Tessent Multi-Die Exam 1  Chapter

Earners of this badge have successfully completed the 50-question exam to show basic knowledge of Multi-die devices and their implementation using Tessent tools

1 Tessent Multi-Die Exam 1 Topic

1. Level 1 Exam - Tessent Multi-Die