Discover & correct problems earlier in the design cycle using advanced simulation techniques to predict how your design will behave.
This workshop explores the pre-layout and post-layout compliance margins using VX 2.12 and simulate IBIS-AMI eye diagrams for final design sign-off
This workshop takes you through an entire SerDes channel compliance design flow from start to finish, including design concepts and HyperLynx usage tips.
In this workshop, you will learn how to run post-layout verification checks in the DDRx design flow using HyperLynx DRC with DDR-focused rules.
This workshop takes you through an entire DDR5 post-layout verification process from start to finish, including design concepts and HyperLynx usage tips.