HyperLynx Video: A Journey Through HyperLynx 1  Chapter

See how to discover and correct problems earlier in your design cycle by using advanced simulation techniques to predict how your completed design will behave.

1 A Journey Through HyperLynx 9 Topics

1. A Journey Through HyperLynx - Introduction
2. DC Drop Power Analysis
3. AC Power Decoupling Analysis
4. Optimizing Decoupling Capacitors
5. Analysis SerDes and Compliance Checking
6. Comprehensive DDRx Analysis with Timing
7. Batch Analysis of High-Speed Nets
8. Electrical Rules Checking
9. Summary - A Journey Through HyperLynx

HyperLynx Workshop: Post-layout PCIe Gen3 Compliance Verification 2  Chapters

Learn pre-layout and post-layout serial link compliance flows to determine system operating margins. Use IBIS-AMI models for Post-route sign-off simulation.

1 Prelayout 3 Topics

1. Explore LineSim file representation of the Channel
2. Optimize channels with 2D models
3. Optimize channels with 3D models

2 Postlayout 3 Topics

1. Optimize and verify compliance margins
2. Verify IBIS AMI eye margins
3. Lab: Post-layout PCIe Gen3 Compliance Verification

HyperLynx Workshop: HyperLynx DRC DDR4-Based Rules 1  Chapter

Learn how to set up and run DDR4-focused rules in HLDRC. Rules-based layout checking is the first step in the HyperLynx Progressive Verification flow.

1 Chapter 1 - HyperLynx DRC DDR4-Based Rules Workshop 3 Topics

1. HyperLynx DRC Overview
2. Demo: HyperLynx DRC DDR4-Based Rules Workshop
3. Lab: HyperLynx DRC DDR4-Based Rules

HyperLynx Workshop: DDR5 Model-free Post-layout Verification 1  Chapter

Learn how to perform DDR5 post-layout verification, even when you don’t have vendor simulation models. Includes design concepts and HyperLynx usage tips.

1 Chapter 1 - HyperLynx and Design Setup 3 Topics

1. HyperLynx DDR5 Overview
2. Demo: DDR5 Model Free Post-Layout Workshop
3. Lab: DDR5 Model Free Post-Layout Workshop

HyperLynx Workshop: DDR4 Power-Aware Workshop 4  Chapters

Learn to set up and simulate a DDR4 interface for operating margins. Create interconnect models that account for non-ideal return signal return paths and SSN.

1 Chapter 1: Design Preparation/Setup 3 Topics

1. Reviewing the DRAM IBIS Model
2. Reviewing the Workshop Designs and Design Settings
3. Lab 1: Design Preparation/Setup

2 Chapter 2: Model Extraction 2 Topics

1. Extracting PDN and Channel Model for a Data Byte Lane
2. Lab 2: Model Extraction

3 Chapter 3: Interactive Simulation 3 Topics

1. Simulating Interactively with Ideal and Non-ideal Models
2. Simulating Eye Diagrams with Ideal and Non-ideal Models
3. Lab 3: Interactive Simulation

4 Chapter 4: DDRx Batch Simulation 5 Topics

1. DDRx Batch Simulation with Ideal and Non-ideal Channel Models
2. DDRx Batch Simulation with Channel Model and Crosstalk
3. DDRx Batch Simulation with PDN & Channel Model
4. DDRx Batch Simulation with PDN & Channel Model and Crosstalk
5. Lab 4:DDRx Batch Simulation

HyperLynx Workshop: Using Design Space Exploration (DSE) to Optimize a Differential Via 3  Chapters

Learn how to use HyperLynx Design Space Exploration to optimize via structures and improve their electrical performance.

1 Chapter 1 - 2D and 3D Via Models 4 Topics

1. Analyzing 2D Via Models for Protocol Compliance
2. Setting Up 3D Via Models
3. Inspecting 3D Via Models and Running Protocol Compliance
4. Lab: Analyze 2D and 3D Differential Via Structures in a PCIE5 channel

2 Chapter 2 - Sweeping Via Parameter Using 3D Explorer 6 Topics

1. Setting Up Differential Via Project in 3D Explorer
2. Excuting Diffenerntial Via Simulation in FWS
3. Excuting Diffenerntial Via Baseline Simulation in 3D Explorer
4. Setting Up Partial Parametric Sweeps in 3D Explorer
5. Setting Up Full Parametric Sweeps in 3D Explorer
6. Lab: Create and solve a 3D model of the Differential Via Structure using 3D Explorer

3 Chapter 3 - Optimizing Differential Via Model Using HyperLynx DSE 9 Topics

1. Exporting to and Setting up an HL DSE Project
2. Adding S-Parameter Export to HLDSE Simulation
3. Running the HL DSE Simulation
4. Compile S-Parameter Files from HL DSE Simulation
5. Inspecting HL DSE Simulation Results
6. Post-Processing HL DSE Results
7. Placing Best Design Set S-Parameters in Schematic
8. Running Compliance Check for PCIE5 Channel with Swept S-Parameters
9. Lab: Export 3D Differential Via structure to HL DSE to achieve a best-case diff via model

HyperLynx Workshop: DC Drop 2  Chapters

Learn to run DC Drop analysis for single and multiple-board systems, make layout changes, and re-run analysis to assess design improvement.

1 HyperLynx DC Drop Overview 1 Topic

1. HyperLynx DC Drop Overview

2 DC Drop Workshop 2 Topics

1. Demo: DC Drop Workshop
2. Lab: DC Drop Workshop

HyperLynx Workshop: HyperLynx Decoupling with AMD Versal Devices 1  Chapter

Learn how to evaluate and optimize AC decoupling performance for an AMD Versal FPGA device based on power estimation data and a detailed package model.

1 Chapter 1 – HyperLynx Decoupling with AMD Versal Devices Workshop 2 Topics

1. Demo: HyperLynx Decoupling with AMD Versal Devices
2. Lab: HyperLynx Decoupling with AMD Versal Devices Workshop

HyperLynx Workshop: Compliance-based Serial Link Design and Verification 6  Chapters

This workshop takes you through an entire SerDes channel compliance design flow from start to finish, including design concepts and HyperLynx usage tips.

1 Chapter 1 - Prelayout Compliance with 2D and 3D Models 5 Topics

1. Initializing tool settings and analyzing the baseline case
2. Exploring via stub length and backdrilling
3. Exploring the effect of 3D via models
4. Exploring 3D modeling of DC blocking Capacitors
5. Comparing the results from progressive analysis

2 Chapter 2 - Prelayout Compliance with Optimized 3D Models 2 Topics

1. Using 3D Explorer to optimize DC blocking capacitors 3D area
2. Running COM analysis by sweeping the S-parameter Files

3 Chapter3 - Prelayout 3D Breakout Modeling 2 Topics

1. Modeling BGA breakout via
2. Modeling connector pins

4 Chapter 4 - Postlayout Single Channel Exploration 3 Topics

1. Initializing tool settings and exploring non-functional pads
2. Exploring the effect of backdrilling in 2D and 3D vias
3. Exploring the effect of surface roughness and crosstalk

5 Chapter 5 - Postlayout Optimization of 3D Structures 2 Topics

1. Setting up a common anti-pad padstack in Advanced Solvers
2. Using 3D Explorer to optimize the DC blocking capacitor area and COM

6 Chapter 6 - Postlayout All Channels Verification 1 Topic

1. Running the final verification

HyperLynx Workshop: Post-layout PCIe Gen3 Compliance Verification – Modern UX 1  Chapter

Learn pre-layout and post-layout serial link compliance flows to determine system operating margins. Use IBIS-AMI models for Post-route sign-off simulation.

1 HyperLynx Workshop: Post-layout PCIe Gen3 Compliance Verification 3 Topics

1. Presentation: HyperLynx Post-layout PCIe Gen3 Compliance Verification Overview
2. Demo: HyperLynx Post-layout PCIe Gen3 Compliance Verification
3. HyperLynx Post-layout PCIe Gen3 Compliance Verification Workshop

HyperLynx Workshop: Design Rule Check (DRC) – DDR4-Based Rules – Modern UX 1  Chapter

Learn how to set up and run DDR4-focused rules in HLDRC. Rules-based layout checking is the first step in the HyperLynx Progressive Verification flow.

1 Chapter 1 – HyperLynx Workshop: Design Rule Check (DRC) – DDR4-Based Rules 3 Topics

1. Presentation: HyperLynx Design Rule Check (DRC) – DDR4-Based Rules Overview
2. Demo: HyperLynx Design Rule Check (DRC) – DDR4-Based Rules
3. Lab: HyperLynx Design Rule Check (DRC) – DDR4-Based Rules Workshop

HyperLynx Workshop: DDR5 Model-free Post-layout Verification – Modern UX 1  Chapter

Learn how to perform DDR5 post-layout verification, even when you don’t have vendor simulation models. Includes design concepts and HyperLynx usage tips.

1 Chapter 1 – HyperLynx Workshop: DDR5 Model-free Post-layout Verification 3 Topics

1. Presentation: HyperLynx DDR5 Verification Overview
2. Demo: HyperLynx DDR5 Model-free Post-layout Verification
3. Lab: HyperLynx DDR5 Model-free Post-layout Verification Workshop

HyperLynx Workshop: DDR4 Power-Aware – Modern UX 1  Chapter

Learn to set up and simulate a DDR4 interface for operating margins. Create interconnect models that account for non-ideal return signal return paths and SSN.

1 Chapter 1 – HyperLynx Workshop: DDR4 Power-Aware 3 Topics

1. Presentation: DDR4 Power-Aware Overview
2. Demo: HyperLynx DDR4 Power-Aware
3. Lab: HyperLynx DDR4 Power-Aware Workshop

Design Space Exploration (DSE) Differential Via Optimization – Modern UX 1  Chapter

Learn how to use HyperLynx Design Space Exploration to optimize via structures and improve their electrical performance.

1 Chapter 1 – HyperLynx Workshop: Design Space Exploration (DSE) Differential Via Optimization 3 Topics

1. Presentation: HyperLynx Design Space Exploration (DSE) Overview
2. Demo: HyperLynx Design Space Exploration (DSE) Differential Via Optimization
3. Lab: HyperLynx Design Space Exploration (DSE) Differential Via Optimization Workshop

HyperLynx Workshop: DC Drop – Modern UX 1  Chapter

Learn to run DC Drop analysis for single and multiple-board systems, make layout changes and re-run analysis to assess design improvement.

1 Chapter 1 – HyperLynx Workshop: DC Drop 3 Topics

1. Presentation: HyperLynx DC Drop Overview
2. Demo: HyperLynx DC Drop
3. Lab: HyperLynx DC Drop Workshop

HyperLynx DC Drop Workshop 1  Chapter

Learn to run DC Drop analysis for single and multiple-board systems, make layout changes and re-run analysis to assess design improvement.

1 HyperLynx DC Drop Workshop 4 Topics

1. Presentation: HyperLynx DC Drop Overview
2. Demo: HyperLynx DC Drop
3. Lab: HyperLynx DC Drop Workshop
4. Try DC Drop on Your Own Design

HyperLynx Workshop: PDN Decoupling with AMD Versal FPGA – Modern UX 1  Chapter

Learn how to evaluate and optimize AC decoupling performance for an AMD Versal FPGA device based on power estimation data and a detailed package model.

1 Chapter 1 – HyperLynx Workshop: PDN Decoupling with AMD Versal FPGA – Modern UX 2 Topics

1. Demo: PDN Decoupling with AMD Versal FPGA – Modern UX
2. Lab: PDN Decoupling with AMD Versal FPGA – Modern UX

HyperLynx Workshop: Compliance-based Serial Link Design and Verification - Modern UX 1  Chapter

This workshop takes you through an entire SerDes channel compliance design flow from start to finish, including design concepts and HyperLynx usage tips.

1 Chapter 1 – HyperLynx Workshop: Compliance-based Serial Link Design and Verification - Modern UX 4 Topics

1. Presentation: Compliance-based Serial Link Design and Verification Overview
2. Demo: Pre-Layout Compliance-based Serial Link Design and Verification Demonstration
3. Demo: Post-Layout Compliance-based Serial Link Design and Verification Demonstration
4. Lab: HyperLynx Compliance-based Serial Link Design and Verification Workshop

HyperLynx Workshop: AMS Parasitic Extraction – Modern UX 1  Chapter

Learn how to use HyperLynx Analog Mixed Signal (AMS) to extract and analyze the effects of post-route parasitic elements on a switching power supply.

1 HyperLynx Workshop: AMS Parasitic Extraction 3 Topics

1. Presentation: HyperLynx AMS Parasitic Extraction Overview
2. Demo: HyperLynx AMS Parasitic Extraction
3. HyperLynx AMS Parasitic Extraction Workshop