On-Demand Training - Explore Design and Verification of Circuits and Systems
Description
A collection of courses and general topics on designing and verifying electronics and electrical circuits and systems and applying EDA tools to automate these tasks. To access this library for free, enter promotional code ExploreVEP__30 in the shopping cart to register.
- 12 month subscription
- Access to cloud-based environment for hands-on lab exercises
- Access to new training content added during the subscription period
- Knowledge assessments to measure learning progress
Explore This On-Demand Training
Chapters
learning path
- Module 0 - DCS: Overview
- Module 1 - DCS: Elements of Logic Circuits, Discrete Design
- Module 2 - DCS: Implementation Methods, Programmable Logic Devices
- Module 3 - DCS: Elements of RT Level Circuit, RTL Design Methodology
- Module 4 - DCS: RTL Components as System Elements, Integration of RTL Components
- Appendix 1 - DCS: Introduction to SystemVerilog
- Appendix 2 - DCS: EDA Tools - ModelSim and Quartus
- Appendix 3 - DCS: Simulation with Questa
- Appendix 4 - Synthesis with Quartus
- Appendix 5 - Synthesis with Yosys
- DCS: Lectures Design Codes and Homework Solutions
Digital Circuits and Systems From Basic Elements to a Complete System
You will learn about digital circuits and systems including design, implementation, and FPGA prototyping of digital circuits and systems focusing on RTL design.
Digital Circuits and Systems From Basic Elements to a Complete System 11 Chapters
You will learn about digital circuits and systems including design, implementation, and FPGA prototyping of digital circuits and systems focusing on RTL design.
1 Module 0 - DCS: Overview 5 Topics
- Course Introduction -Topic 0
- Course Introduction -Topic 0
- Digital Design Flow -Topic 1
- Digital Design Flow -Topic 1
- Homework - Topic 1
2 Module 1 - DCS: Elements of Logic Circuits, Discrete Design 36 Topics
- Number Systems -Topic 2
- Number Systems -Topic 2
- Homework - Topic 2
- Transistor to Gates -Topic 3A
- Transistor to Gates -Topic 3B
- Transistor to Gates -Topic 3C
- Transistor to Gates -Topic 3D
- Transistor to Gates -Topic 3
- Homework -Topic 3
- Gates and Logic Minimization -Topic 4A
- Gates and Logic Minimization -Topic 4B
- Gates and Logic Minimization -Topic 4C
- Gates and Logic Minimization -Topic 4D
- Gates and Logic Minimization -Topic 4E
- Gates and Logic Minimization -Topic 4
- Homework -Topic 4
- Combinational Elements -Topic 5A
- Combinational Elements -Topic 5B
- Combinational Elements -Topic 5C
- Combinational Elements -Topic 5D
- Combinational Elements -Topic 5E
- Combinational Elements -Topic 5F
- Combinational Elements -Topic 5
- Homework -Topic 5
- Sequential Elements -Topic 6A
- Sequential Elements -Topic 6B
- Sequential Elements -Topic 6C
- Sequential Elements -Topic 6D
- Sequential Elements -Topic 6
- Homework -Topic 6
- Finite State Machines -Topic 7A
- Finite State Machines -Topic 7B
- Finite State Machines -Topic 7C
- Finite State Machines -Topic 7D
- Finite State Machines -Topic 7
- Homework -Topic 7
3 Module 2 - DCS: Implementation Methods, Programmable Logic Devices 11 Topics
- PLD Transistors and Gates -Topic 8A
- PLD Transistors and Gates -Topic 8B
- PLD Transistors and Gates -Topic 8C
- PLD Transistors and Gates -Topic 8
- Homework -Topic 8
- Complex PLD Structures -Topic 9
- Complex PLD Structures -Topic 9
- Homework -Topic 9
- FPGA Structure- Topic 10
- FPGA Structure- Topic 10
- Homework -Topic 10
4 Module 3 - DCS: Elements of RT Level Circuit, RTL Design Methodology 33 Topics
- RTL Datapath and Controller -Topic 11A
- RTL Datapath and Controller -Topic 11B
- RTL Datapath and Controller -Topic 11
- Homework -Topic 11
- Combinational RTL Elements -Topic 12A
- Combinational RTL Elements -Topic 12B
- Combinational RTL Elements -Topic 12C
- Combinational RTL Elements -Topic 12D
- Combinational RTL Elements -Topic 12E
- Combinational RTL Elements -Topic 12
- Homework -Topic 12
- Sequential RTL Elements -Topic 13A
- Sequential RTL Elements -Topic 13B
- Sequential RTL Elements -Topic 13C
- Sequential RTL Elements -Topic 13D
- Sequential RTL Elements -Topic 13
- Homework -Topic 13
- FSMs as Controllers -Topic 14A
- FSMs as Controllers -Topic 14B
- FSMs as Controllers -Topic 14C
- FSMs as Controller -Topic 14
- Homework -Topic 14
- RTL Design Methodology -Topic 15A
- RTL Design Methodology -Topic 15B
- RTL Design Methodology -Topic 15C
- RTL Design Methodology -Topic 15D
- RTL Design Methodology -Topic 15E
- RTL Design Methodology -Topic 15F
- RTL Design Methodology -Topic 15
- Homework -Topic 15
- Designing RTL IP Cores -Topic 16
- Designing RTL IP Cores -Topic 16
- Homework -Topic 16
5 Module 4 - DCS: RTL Components as System Elements, Integration of RTL Components 13 Topics
- Embedded System Hardware- Topic 17
- Embedded System Hardware- Topic 17
- Bussing and Memory Mapped Structure -Topic 18A
- Bussing and Memory Mapped Structure -Topic 18B
- Bussing and Memory Mapped Structure -Topic 18
- Homework -Topic 17&18
- Processing Elements and Wrappers -Topic 19A
- Homework -Topic 19A
- Processing Elements and Wrappers -Topic 19B
- Processing Elements and Wrappers -Topic 19
- Direct Memory Access (DMA) -Topic 20
- Direct Memory Access (DMA) -Topic 20
- Homework -Topic 20
6 Appendix 1 - DCS: Introduction to SystemVerilog 4 Topics
- Introduction to SystemVerilog - Part A
- Introduction to SystemVerilog - Part B
- Introduction to SystemVerilog - Part C
- Introduction to SystemVerilog - Appendix 1
7 Appendix 2 - DCS: EDA Tools - ModelSim and Quartus 4 Topics
- ModelSim and Quartus -Part A
- ModelSim anad Quartus -Part B
- ModelSim anad Quartus -Part C
- EDA Tools ModelSim and Quartus -Appendix 2
8 Appendix 3 - DCS: Simulation with Questa 2 Topics
- Simulation with Questa
- Simulation with Questa -Appendix 3
9 Appendix 4 - Synthesis with Quartus 2 Topics
- Synthesis with Quartus
- Synthesis with Quartus -Appendix 4
10 Appendix 5 - Synthesis with Yosys 2 Topics
- Synthesis with Yosis
- Synthesis with Yosis -Appendix 5
11 DCS: Lectures Design Codes and Homework Solutions 32 Topics
- Module 0 - Topic 1 Homework Solution
- Module 1 - Topic 2 Homework Solution
- Module 1 - Topic 3 Homework Solution
- Module 1 - Topic 4 Homework Solution
- Module 1 - Topic 4E Homework Code
- Module 1 - Topic 5 Homework Solution
- Module 1 - Topic 5E Homework Code
- Module 1 - Topic 6 Homework Solution
- Module 1 - Topic 7 Homework Solution
- Module 1 - Topic 7D Homework Code
- Module 2 - Topic 8 Homework Solution
- Module 2 - Topic 9 Homework Solution
- Module 2 - Topic 10 Homework Solution
- Module 3 - Topic 11 Homework Solution
- Module 3 - Topic 12 Homework Solution
- Module 3 - Topic 12A Homework Code
- Module 3 - Topic 12B Homework Code
- Module 3 - Topic 12C Homework Code
- Module 3 - Topic 12D Homework Code
- Module 3 - Topic 12E Homework Code
- Module 3 - Topic 13 Homework Solution
- Module 3 - Topic 13B Homework Code
- Module 3 - Topic 14 Homework Solution
- Module 3 - Topic 14A Homework Code
- Module 3 - Topic 14C Homework Code
- Module 3 - Topic 15 Homework Solution
- Module 3 - Topic 16 Homework Solution
- Module 3 - Topic 16 Homework Code
- Module 4 - Topic 17_18 Homework Solution
- Module 4 - Topic 19 Homework Solution
- Module 4 - Topic 20 Homework Solution
- DCS Lectures Design Codes
Chapters
learning path
- Introduction
- Session 1: Verification Process Overview
- Session 2: Creating and Using a Test Plan
- Session 3: Data Types and Procedural Statements
- Session 4: Creating and Using Functional Coverage
- Session 5: Creating and Using Constrained Random
- Session 6: Connecting the Test Bench to the Design
- Session 7: Execution Semantics and Synchronization
- Session 8: Object-Oriented Programming in SV
- Session 9: Test Bench Customization in UVM
- Session 10: UVM Stimulus, Tests, and Regressions
Functional Verification of Digital Logic
You will learn essential verification techniques, from setting up test plans to applying UVM, and managing inter-process communications.
Functional Verification of Digital Logic 11 Chapters
You will learn essential verification techniques, from setting up test plans to applying UVM, and managing inter-process communications.
1 Introduction 1 Topic
- FVDL Meet the Instructors
2 Session 1: Verification Process Overview 11 Topics
- FVDL Verification Process Overview: Introduction
- Verification Process Overview: Introduction
- FVDL Understanding the Two Main Testing Approaches
- Verification Process Overview: Understanding the Two Main Testing Approaches
- FVDL What Is a Reusable Testbench?
- Verification Process Overview: What is a Reusable Testbench?
- FVDL How Can I Reuse Testbench Components?
- Verification Process Overview: How Can I Reuse Testbench Components?
- FVDL UVM Test Flow
- Verification Process Overview: UVM Test Flow
- Session 1 Training Resources
3 Session 2: Creating and Using a Test Plan 5 Topics
- FVDL Creating a Test Plan
- Creating and Using a Test Plan: Creating a Test Plan
- FVDL Test Plan Fields
- Creating and Using a Test Plan: Test Plan Fields
- Session 2 Training Resources
4 Session 3: Data Types and Procedural Statements 9 Topics
- FVDL SystemVerilog Data Types
- Data Types and Procedural Statements: SystemVerilog Data Types
- FVDL Multidimensional Arrays
- Data Types and Procedural Statements: Multidimensional Arrays
- FVDL Built-In Unpacked Arrays
- Data Types and Procedural Statements: Built-In Unpacked Arrays
- FVDL Procedural Programming Statements
- Data Types and Procedural Statatements: Procedural Programming Statements
- Session 3 Training Resources
5 Session 4: Creating and Using Functional Coverage 9 Topics
- FVDL Introduction to Functional Coverage
- Creating and Using Functional Coverage: Introduction to Functional Coverage
- FVDL SystemVerilog Coverage Constructs
- Creating and Using Functional Coverage: SystemVerilog Coverage Constucts
- FVDL Reusable Coverage, Reporting, and Options
- Creating and Using Functional Coverage: Reusable Coverage, Reporting, and Options
- FVDL Sampling and Using Coverage
- Creating and Using Functional Coverage: Sampling and Using Coverage
- Session 4 Training Resources
6 Session 5: Creating and Using Constrained Random 11 Topics
- FVDL Introduction to Constrained-Random Stimulus
- Creating and Using Constrained Random: Introduction to Constrained-Random Stimulus
- FVDL Verilog Expression Impact on Constraints
- Creating and Using Constrained Random: Verilog Expression Impact on Constraints
- FVDL Issues Contributing to Randomization Failures
- Creating and Using Constrained Random: Issues Contributing to Randomization Failures
- FVDL Random Stimulus Probabilities and Statistics
- Creating and Using Constrained Random: Random Stimulus Probabilities and Statistics
- FVDL Random Variable and Constraint Features
- Creating and Using Constrained Random: Random Variable and Constraint Features
- Session 5 Training Resources
7 Session 6: Connecting the Test Bench to the Design 7 Topics
- FVDL Connecting the DUT and Test Bench
- Connecting the Test Bench to the Design: Connecting the DUT and Test Bench
- FVDL Interface Ports, Timing, and Direction
- Connecting the Test Bench to the Design: Interface Ports, Timing, and Direction
- FVDL Implementing Protocol Signaling
- Connecting the Test Bench to the Design: Implementing Protocol Signaling
- Session 6 Training Resources
8 Session 7: Execution Semantics and Synchronization 7 Topics
- FVDL Timing and Execution Semantics
- Execution Semantics and Synchronization: Timing and Execution Semantics
- FVDL Threads
- Execution Semantics and Synchronization: Threads
- FVDL Semaphores and Mailboxes
- Execution Semantics and Synchronization: Semaphores and Mailboxes
- Session 7 Training Resources
9 Session 8: Object-Oriented Programming in SV 17 Topics
- FVDL Introduction to Classes in SystemVerilog
- SystemVerilog OOP for UVM Verification: Introduction to Classes in SystemVerilog
- FVDL Class Basics
- SystemVerilog OOP for UVM Verification: Class Basics
- FVDL Class Properties and Methods
- SystemVerilog OOP for UVM Verification: Class Properties and Methods
- FVDL Static Properties, Methods, and List
- SystemVerilog OOP for UVM Verification: Static Properties, Methods, and List
- FVDL Inheritance
- SystemVerilog OOP for UVM Verification: Inheritance
- FVDL Polymorphism
- SystemVerilog OOP for UVM Verification: Polymorphism
- FVDL Design Patterns and Parameterized Classes
- SystemVerilog OOP for UVM Verification: Design Patterns and Parameterized Classes
- FVDL Design Patterns Examples
- Object-Oriented Programming in SV: Design Patterns Examples
- Session 8 Training Resources
10 Session 9: Test Bench Customization in UVM 7 Topics
- FVDL What Is the UVM Factory
- Configuring a UVM Test Bench: What is the UVM Factory?
- FVDL Using the UVM Factory
- Configuring a UVM Test Bench: Using the UVM Factory
- FVDL Using the UVM Configuration Database
- Configuring a UVM Test Bench: Using the UVM Configuration Database
- Session 9 Training Resources
11 Session 10: UVM Stimulus, Tests, and Regressions 9 Topics
- FVDL How Do We Write a UVM Test?
- Running a Test in UVM: How Do I Write a UVM Test?
- FVDL How Do I Model Communication?
- Running a Test in UVM: How Do I Model Communication?
- FVDL How Do I Stimulate My Design
- Running a Test in UVM: How Do I Stimulate My Design?
- FVDL How Do I Create Complex Test Scenarios?
- Running a Test in UVM: How Do I Create Complex Test Scenarios?
- Session 10 Training Resources
Chapter
learning path
- Final Assessment
Functional Verification of Digital Logic Certification Exam
Functional Verification of Digital Logic Certification Exam - Take and pass this exam to earn a digital badge.
Functional Verification of Digital Logic Certification Exam 1 Chapter
Functional Verification of Digital Logic Certification Exam - Take and pass this exam to earn a digital badge.
1 Final Assessment 1 Topic
- Final Assessment
On-Demand Training - Explore Design and Verification of Circuits and Systems
Receive unlimited access to all new content added during your active subscription.
During your subscription period, you will automatically receive access to all new content added to the library, including training on new product releases and technology updates to maximize your proficiency.
On-Demand Training - Explore Design and Verification of Circuits and Systems
- 12 month subscription
- Access to cloud-based environment for hands-on lab exercises
- Access to new training content added during the subscription period
- Knowledge assessments to measure learning progress
Starting at
USD $2500.00 / year
USD $2500.00 / year