Learning Center Overview and Functional Verification Curriculum 1  Chapter

Learn how to navigate the Learning Center and view curriculum maps for Functional Verification Library.

1 Learning Center Overview and Functional Verification Curriculum 3 Topics

1. Learning Center Overview
2. Video, Quiz, and Lab Times
3. Learning Paths Overview and Curriculums

SystemVerilog for Verification 13  Chapters

Learn about SystemVerilog basics and advanced verification capabilities such as object oriented programming, constrained random testing and functional coverage.

1 SystemVerilog Concepts and Guidelines 12 Topics

1. SystemVerilog Verification Introduction
2. SystemVerilog Random Verification
3. SystemVerilog Coverage
4. SystemVerilog Levels of Abstraction
5. Knowledge Check 1: SystemVerilog Concepts and Guidelines
6. SystemVerilog Compiler Directives
7. SystemVerilog Time and Delays
8. SystemVerilog System Tasks and Function
9. SystemVerilog Testbench Organization
10. Knowledge Check 2: SystemVerilog Concepts and Guidelines
11. Lab: SystemVerilog Simulate and Debug a 1-bit Adder
12. Assessment: SystemVerilog Concepts and Guidelines

2 SystemVerilog Syntax and Data Types 17 Topics

1. SystemVerilog Syntax
2. SystemVerilog Literals
3. SystemVerilog Data Types and Value Sets
4. SystemVerilog Vectors
5. Knowledge Check 1: SystemVerilog Syntax and Data Types
6. SystemVerilog Enumerated Types
7. SystemVerilog User Defined Types
8. SystemVerilog Casting
9. Knowledge Check 2: SystemVerilog Syntax and Data Types
10. SystemVerilog Hierarchical References
11. SystemVerilog Port Declaration
12. SystemVerilog Port Connections
13. SystemVerilog Parameters and Constants
14. SystemVerilog Structures
15. Knowledge Check 3: SystemVerilog Syntax and Data Types
16. Lab: SystemVerilog Using 4-State and 2-State Types
17. Assessment: SystemVerilog Syntax and Data Types

3 SystemVerilog Procedural Blocks and Statements 13 Topics

1. SystemVerilog Initial and Always Blocks
2. SystemVerilog Event Simulation
3. SystemVerilog Blocking and Non-blocking Assignment Statements
4. SystemVerilog Continuous Assignment Statements
5. SystemVerilog Force and Release
6. Knowledge Check 1: SystemVerilog Procedural Blocks and Statements
7. SystemVerilog Tasks and Functions
8. SystemVerilog Subroutine Arguments
9. SystemVerilog Subroutine Storage
10. SystemVerilog Ref Arguments and Defaults
11. Knowledge Check 2: SystemVerilog Procedural Blocks and Statements
12. Lab: SystemVerilog Model and Verify a Johnson Counter
13. Assessment: SystemVerilog Procedural Blocks and Statements

4 SystemVerilog Programming Statements 10 Topics

1. SystemVerilog If and Assert Statements
2. SystemVerilog Case Statement
3. SystemVerilog Forever, Repeat, and While Loops
4. Knowledge Check 1: SystemVerilog Programming Statements
5. SystemVerilog For-loop and Foreach-loops
6. SystemVerilog Block Names and Loop Control
7. SystemVerilog File I/O
8. Knowledge Check 2: SystemVerilog Programming Statements
9. Lab: SystemVerilog Model and Verify a BCD Encoder
10. Assessment: SystemVerilog Programming Statements

5 SystemVerilog Operators and Operation Rules 15 Topics

1. SystemVerilog Operators Introduction
2. SystemVerilog Bitwise and Unary-Reduction Operators
3. SystemVerilog Logical and Comparison Operators
4. SystemVerilog Equality Operators
5. SystemVerilog Inside Operator
6. Knowledge Check 1: SystemVerilog Operators
7. SystemVerilog Conditional Operator
8. SystemVerilog Arithmetic Operators
9. SystemVerilog Shift and Concatenate Operators
10. SystemVerilog Assignment Operator
11. SystemVerilog Operation Size
12. SystemVerilog Streaming Operators
13. Knowledge Check 2: SystemVerilog Operators
14. Lab: SystemVerilog Model and Verify an ALU
15. Assessment: SystemVerilog Operators

6 SystemVerilog Arrays and Packages 18 Topics

1. SystemVerilog Vectors and Arrays
2. SystemVerilog Array Assignment and Comparison
3. SystemVerilog Arrays Literals
4. Knowledge Check 1: SystemVerilog Arrays and Packages
5. SystemVerilog Dynamic Arrays
6. SystemVerilog Strings
7. SystemVerilog Queues
8. Knowledge Check 2: SystemVerilog Arrays and Packages
9. SystemVerilog Associative Arrays
10. SystemVerilog Basic Array Methods
11. SystemVerilog Advanced Array Methods
12. Knowledge Check 3: SystemVerilog Arrays and Packages
13. SystemVerilog Scoreboards
14. SystemVerilog Packages
15. SystemVerilog Package Import
16. Knowledge Check 4: SystemVerilog Arrays and Packages
17. Lab: SystemVerilog Arrays and Packages
18. Assessment: SystemVerilog Arrays and Packages

7 SystemVerilog Interfaces and Ports 9 Topics

1. SystemVerilog Ports and Interfaces
2. SystemVerilog Interface Signals, Methods, and Ports
3. SystemVerilog Modports
4. Knowledge Check 1: SystemVerilog Interfaces
5. SystemVerilog Parameterized Interfaces
6. SystemVerilog Connecting with Interfaces
7. Knowledge Check 2: SystemVerilog Interfaces
8. Lab: Verify With Testbench Interfaces
9. Assessment: SystemVerilog Interfaces

8 SystemVerilog Basic OOP 18 Topics

1. SystemVerilog Introduction to Object Oriented Programming
2. SystemVerilog Introduction to Classes
3. SystemVerilog Questa GUI OOP Debug
4. SystemVerilog Constructors
5. Knowledge Check 1: SystemVerilog Basic OOP
6. SystemVerilog Handles and Objects Part 1
7. SystemVerilog Handles and Objects Part 2
8. SystemVerilog Shallow Object Copy
9. SystemVerilog Deep Object Copy
10. SystemVerilog Cloning Objects
11. Knowledge Check 2: SystemVerilog Basic OOP
12. SystemVerilog Class Declaration Details
13. SystemVerilog Static Properties and Methods
14. SystemVerilog Verification Classes
15. SystemVerilog Virtual Interfaces
16. Knowledge Check 3: SystemVerilog Basic OOP
17. Lab: SystemVerilog Basic OOP
18. Assessment: SystemVerilog Basic OOP

9 SystemVerilog Advanced OOP 15 Topics

1. SystemVerilog Class Extension
2. SystemVerilog Advanced OOP Terminology
3. SystemVerilog Transaction Generator
4. SystemVerilog Handles and Objects Part 3
5. Knowledge Check 1: SystemVerilog Advanced OOP
6. SystemVerilog Virtual Methods
7. SystemVerilog Method Prototype
8. Knowledge Check 2: SystemVerilog Advanced OOP
9. SystemVerilog Generator and Virtual Methods
10. SystemVerilog Advanced Constructors
11. SystemVerilog Parameterized Classes
12. SystemVerilog Class Member Visibility
13. Knowledge Check 3: SystemVerilog Advanced OOP
14. Lab: SystemVerilog Advanced OOP
15. Assessment: SystemVerilog Advanced OOP

10 SystemVerilog Constrained Random Generation 18 Topics

1. SystemVerilog Class-Based Randomization
2. SystemVerilog Randomization Example
3. SystemVerilog Constraint Solver
4. SystemVerilog Membership, Distribution, and Unique Constraints
5. Knowledge Check 1: SystemVerilog Constrained Random Generation
6. SystemVerilog Implication Constraint
7. SystemVerilog Randomizing Arrays
8. SystemVerilog Randomizing Composite Objects
9. SystemVerilog Random Distribution and probability
10. SystemVerilog Constraint Inheritance and In-line Constraints
11. Knowledge Check 2: SystemVerilog Constrained Random Generation
12. SystemVerilog Soft Constraints
13. SystemVerilog Randomization Setup and Cleanup
14. SystemVerilog Random Cyclic Variables
15. SystemVerilog Randomization Issues and Alternatives
16. Knowledge Check 3: SystemVerilog Constrained Random Generation
17. Lab: SystemVerilog Constrained Randomization
18. Assessment: SystemVerilog Constrained Random Generation

11 SystemVerilog Functional Coverage 16 Topics

1. SystemVerilog Coverage Comparison
2. SystemVerilog Functional Coverage Strategies
3. SystemVerilog Functional Coverage Flow
4. SystemVerilog Covergroup Definition
5. Knowledge Check 1: SystemVerilog Functional Coverage
6. SystemVerilog Sampling and Conditional Coverage
7. SystemVerilog Coverpoint Bins
8. SystemVerilog Special Coverage Bins
9. Knowledge Check 2: SystemVerilog Functional Coverage
10. SystemVerilog Cross Coverage
11. SystemVerilog Generic Covergroups
12. SystemVerilog Coverage Options
13. SystemVerilog Coverage Methods
14. Knowledge Check 3: SystemVerilog Functional Coverage
15. Lab: SystemVerilog Functional Coverage
16. Assessment: SystemVerilog Functional Coverage

12 SystemVerilog Threads and Interprocess Communication 13 Topics

1. SystemVerilog Introduction to Interprocess Communication
2. SystemVerilog Fork-Join
3. SystemVerilog Fork-Join_none
4. SystemVerilog Fork-Join_any
5. Knowledge Check 1: SystemVerilog Threads and Interprocess Communication
6. SystemVerilog Disable Threads
7. SystemVerilog Spawning Threads in a Loop
8. Knowledge Check 2: SystemVerilog Threads and Interprocess Communication
9. SystemVerilog Events and Semaphores
10. SystemVerilog Mailboxes
11. Knowledge Check 3: SystemVerilog Threads and Interprocess Communication
12. Lab: SystemVerilog Threads and Interprocess Communication
13. Assessment: SystemVerilog Threads and Interprocess Communication

13 SystemVerilog for Verification Exam 1 Topic

1. Level 1 Exam - SystemVerilog for Verification

SystemVerilog UVM 9  Chapters

In this learning path you will learn how to use the Universal Verification Methodology (UVM) to create reusable verification environments.

1 UVM Overview 18 Topics

1. UVM Glossary and OOP Review
2. UVM Methodology
3. UVM What UVM Provides
4. Knowledge Check 1: UVM Overview
5. UVM Topology and Class Hierarchy
6. UVM Phases
7. Knowledge Check 2: UVM Overview
8. UVM Hello World Example
9. UVM Example: Transactions and Driver
10. UVM Example: Agent, Environment and Test Class
11. UVM Example: Running a Test
12. Knowledge Check 3: UVM Overview
13. UVM Factory
14. UVM Messaging
15. UVM Debugging and Documentation
16. Knowledge Check 4: UVM Overview
17. Lab: First Look at SystemVerilog UVM
18. Assessment: UVM Overview

2 UVM Transactions and Sequences 14 Topics

1. UVM Stimulus Introduction
2. UVM Transaction Coding Style
3. UVM Transaction Methods
4. Knowledge Check 1: UVM Transactions and Sequences
5. UVM copy() and compare() Methods
6. UVM convert2string() and Other do Methods
7. UVM Extended Transaction Classes and Guidelines
8. Knowledge Check 2: UVM Transactions and Sequences
9. UVM Sequences Introduction
10. UVM Test, Sequence, and Driver Handshake
11. UVM Sequences Summary
12. Knowledge Check 3: UVM Transactions and Sequences
13. Lab: UVM Transactions and Sequences
14. Assessment: UVM Transactions and Sequences

3 UVM Drivers and Sequencers 6 Topics

1. UVM TLM Communication
2. UVM Drivers and Sequencers
3. UVM Interfaces and Emulation
4. Knowledge Check 1: UVM Drivers and Sequencers
5. Lab: UVM Sequencers and Drivers
6. Assessment: UVM Drivers and Sequencers

4 UVM Monitors and Agents 8 Topics

1. UVM Monitors Introduction
2. UVM TLM Analysis Ports
3. UVM Monitor Example
4. UVM Agents Introduction
5. UVM Agents Example
6. Knowledge Check: UVM Monitors and Agents
7. Lab: UVM Monitors and Agents
8. Assessment: UVM Monitors and Agents

5 UVM Coverage Collectors 5 Topics

1. UVM Coverage Collector Introduction
2. UVM Coverage Collector Example
3. Knowledge Check: UVM Coverage Collectors
4. Lab: UVM Coverage Collector
5. Assessment: UVM Coverage Collectors

6 UVM Scoreboards and Environments 8 Topics

1. UVM Scoreboards Introduction
2. UVM Scoreboards Internals
3. UVM Scoreboards Hierarchical Example
4. UVM Scoreboards Flat Example
5. UVM Environments
6. Knowledge Check 1: UVM Scoreboards and Environments
7. Lab: UVM Scoreboards
8. Assessment: UVM Scoreboards

7 UVM Configuration and Factory 12 Topics

1. UVM Configuration Introduction
2. UVM Configuration HDL to Test Example
3. UVM Configuration Objects
4. UVM Configuration Test to Environment Example
5. Knowledge Check 1: UVM Configuration
6. UVM Configuration Agent to Monitor Example
7. UVM Configuration Sequences, Arrays and Debug
8. UVM Factory Introduction
9. UVM Factory Override Examples
10. Knowledge Check 2: UVM Configuration and Factory
11. Lab: UVM Configuration and Factory
12. Assessment: UVM Configuration and Factory

8 UVM Tests and Complex Sequences 13 Topics

1. UVM Tests Architecture
2. UVM Tests Sharing Sequencer Handles
3. UVM Tests Controlling the Run Phase
4. UVM Complex Sequences Single Protocol
5. Knowledge Check 1: UVM Tests and Complex Sequences
6. UVM Complex Sequences Multiple Protocols
7. UVM Complex Sequences Arbitration Overview
8. UVM Complex Sequences Arbitration Algorithms
9. UVM Complex Sequences Parallel and Layered Sequences
10. UVM Complex Sequences Driver Synchronization
11. Knowledge Check 2: UVM Tests and Complex Sequences
12. Lab: UVM Tests and Virtual Sequences
13. Assessment: UVM Tests and Complex Sequences

9 SystemVerilog UVM Exam 1 Topic

1. Level 1 Exam - SystemVerilog UVM

UVM Intermediate 6  Chapters

Create a UVM Register Layer description of hardware registers and memories, integrate into a UVM testbench, and verify your design with methods and sequences.

1 UVM Intermediate Learning Path Overview 1 Topic

1. Learning Path Overview

2 Register Layer Overview 4 Topics

1. UVM Intermediate: Register Layer Introduction
2. UVM Intermediate: Register Block Concepts
3. UVM Intermediate: Register Layer Flow
4. Assessment: Register Layer Overview

3 Register Description 5 Topics

1. UVM Intermediate: Questa Register Assistant Flow
2. UVM Intermediate: Questa Register Assistant Inputs
3. UVM Intermediate: Questa Register Assistant Results
4. Lab: Register Description
5. Assessment: Register Description

4 Register Model Integration 6 Topics

1. UVM Intermediate: Integration Overview
2. UVM Intermediate: Register Model Adapter
3. UVM Intermediate: Register Model Prediction
4. UVM Intermediate: Register Integration Example
5. Lab: Integrating Register Model
6. Assessment: Register Description

5 Applying the Register Model Layer 14 Topics

1. UVM Intermediate: Apply Register Model Introduction
2. UVM Intermediate: Register Methods 1
3. UVM Intermediate: Register Methods 2
4. UVM Intermediate: Checking Registers
5. UVM Intermediate: Memories
6. UVM Intermediate: Introspection Methods
7. Knowledge Check 1: Apply Register Model
8. Lab: Apply the Register Model Layer
9. UVM Intermediate: Quirky Registers
10. UVM Intermediate: Functional Coverage
11. UVM Intermediate: Predefined Sequences
12. Knowledge Check 2: Apply Register Model
13. Lab: Quirky Registers
14. Assessment: Apply Register Model

6 UVM Intermediate Exam 1 Topic

1. Level 1 Exam - UVM Intermediate

UVM Advanced 2  Chapters

Learn advanced UVM features for creating and controlling testbench components, configuration, and generating complex stimuli

1 UVM Styles and Reusability 8 Topics

1. Concepts and Reuse
2. Transactions Styles
3. Knowledge Check 1-1: Styles and Reusability
4. Virtual Sequences and Sequencers
5. Testbench Styles
6. UVM Versions
7. Knowledge Check 1-2: Testbench Styles and UVM Versions
8. Assessment: UVM Styles and Reusability

2 UVM Utilities 13 Topics

1. Containers: uvm_queue
2. Containers: uvm_pool
3. Knowledge Check 2-1: uvm_queue and uvm_containers
4. Synchronization with uvm_event
5. Synchronization with uvm_barrier
6. Knowledge Check 2-2: uvm_event and uvm_barrier
7. UVM Factory
8. Hook Methods
9. Callbacks
10. Ending Simulation
11. Knowledge Check 2-3: UVM Factory, hook methods, callbacks and ending simulation
12. Lab: UVM Utilities
13. Assessment: UVM Utilities

UVM Framework 8  Chapters

Learn how to quickly build sophisticated UVM testbenches with UVM Framework, a class library and code generator, part of the Questa® Verification Solution.

1 UVM Framework Learning Path Overview 1 Topic

1. Learning Path Overview

2 UVM Framework: Introduction 4 Topics

1. UVM Framework: Introduction
2. UVM Framework: Design Under Test
3. UVM Framework: Plan Stimulus and Checks
4. Assessment: UVM Framework Introduction

3 UVM Framework: Create Interface 5 Topics

1. UVM Framework: Describe the Input Protocol Interface
2. UVM Framework: Generate the Input Protocol Interface
3. UVM Framework: Create the Output Protocol Interface
4. Lab: UVM Framework: Create Interface
5. Assessment: UVM Framework: Create Interface

4 UVM Framework: Create Environment 3 Topics

1. UVM Framework: Describe the Environment
2. UVM Framework: Generate the Environment
3. Assessment: UVM Framework: Create Environment

5 UVM Framework: Create Bench 4 Topics

1. UVM Framework: Bench Description
2. UVM Framework: Bench Generation
3. Lab: UVM Framework: Create Bench
4. Assessment: UVM Framework: Create Bench

6 UVM Framework: Complete the Bench 10 Topics

1. UVM Framework: Simulate the Out of the Box Bench
2. Lab: Out of the Box Simulation
3. UVM Framework: Connect the DUT and Bench
4. Lab: Connect the DUT and Bench
5. UVM Framework: Drive and Monitor Input Transactions
6. UVM Framework: Drive and Monitor Output Transactions
7. Lab: Drive and Monitor Transactions
8. UVM Framework: Predict the Results
9. Lab: Predict the Results
10. Assessment: UVM Framework: Complete the Bench

7 UVM Framework: Start Verification 4 Topics

1. UVM Framework: Create a New Test and Transaction
2. UVM Framework: Configuration and Sequences
3. Lab: Start Verification of DUT
4. Assessment: Start Verification

8 UVM Framework Exam 1 Topic

1. Level 1 Exam - UVM Framework

Questa Verification IP (QVIP) 4  Chapters

Learn how to create stimulus and check results for standard protocols with Questa Verification IP. Build a UVM testbench or add QVIP to an existing one.

1 QVIP Overview 6 Topics

1. QVIP Introduction
2. QVIP Flows
3. Design Under Test
4. AXI Introduction
5. Knowledge Check 1: QVIP Overview
6. Assessment: QVIP Overview

2 QVIP Master: Verify RTL Slave 9 Topics

1. Configurator Inputs 1
2. Configurator Inputs 2
3. Configurator Outputs
4. Knowledge Check 1: QVIP Master
5. Compile and Debug
6. Create New Stimulus
7. Knowledge Check 2: QVIP Master
8. Lab 1: QVIP Master
9. Assessment: QVIP Master

3 QVIP Slave: Verify RTL Master 7 Topics

1. Introduction
2. Connect and Configure
3. Stimulus and Checks
4. Knowledge Check 1: QVIP Slave
5. Lab 2: QVIP Slave
6. Lab 3: QVIP Advanced
7. Assessment: QVIP Slave

4 Questa Verification IP Exam 1 Topic

1. Level 1 Certification - Questa Verification IP

UVM Framework QVIP Integration 7  Chapters

Learn how to build a UVM testbench for an IP core using UVM Framework and Questa Verification IP (QVIP).

1 Introduction to UVM Framework QVIP Integration 1 Topic

1. Introduction to UVMF and QVIP

2 Creating the DUT 3 Topics

1. Generating the DUT
2. Lab: Creating the DUT
3. Assessment: Creating the DUT

3 Creating the SVVA Testbench 3 Topics

1. Creating the Testbench Project
2. Lab: Creating SVVA Testbench
3. Assessment: Creating SVVA Testbench

4 Generating the QVIP Interface 3 Topics

1. Creating the QVIP Environment
2. Lab: Creating the QVIP Environment
3. Assessment: Generating the QVIP Interface

5 Generating the UVMF Testbench 3 Topics

1. Generating the UVMF Testbench
2. Lab: Generating the UVMF Testbench
3. Assessment: Generating the UVMF Testbench

6 Importing the UVMF Testbench 3 Topics

1. Importing the Generated UVMF Code Into a SVVA Project
2. Lab: Importing the UVMF Testbench
3. Assessment: Importing the UVMF Testbench

7 Completing the Testbench 3 Topics

1. Completing & Simulating the UVMF Testbench
2. Lab: Completing the Testbench
3. Assessment: Completing the Testbench

Questa Core HDL Simulation 7  Chapters

Learn how to use Questa GUI and command line to verify and debug HDL designs in interactive mode or build batch mode scripts for fast simulations.

1 Questa HDL Simulation Learning Path Overview 1 Topic

1. Learning Path Overview

2 Questa Introduction to Simulation 11 Topics

1. Questa: Simulation in the Digital Design Flow
2. Questa: Simulation Process
3. Knowledge Check 1: Questa Introduction to Simulation
4. Questa: Overview of Features and Supported Industry Standards
5. Questa: Modes of Operation
6. Visualizer: Typical Usage Flows
7. Knowledge Check 2: Questa Introduction to Simulation
8. Questa/Visualizer: Getting help
9. Knowledge Check 3: Questa Introduction to Simulation
10. Lab 1: Questa Documentation and Help
11. Assessment: Questa Introduction to Simulation

3 Questa Basic Simulation Using Commands 12 Topics

1. Questa: Command Line Overview
2. Questa: Libraries and Design Units
3. Knowledge Check 1: Questa Basic Simulation Using Commands
4. Questa: Compilation and Optimization commands
5. Questa: Optimization with QIS Flow
6. Questa: QIS Flow Examples
7. Questa: Basic Simulation Commands
8. Knowledge Check 2: Questa Basic Simulation Using Commands
9. Questa: Simple Stimulus Using Simulator
10. Knowledge Check 3: Questa Basic Simulation Using Commands
11. Lab 2: Questa Command Line Simulation
12. Assessment: Questa Basic Simulation Using Commands

4 Visualizer Graphical User Interface 18 Topics

1. Visualizer: Overview of GUI Operation
2. Visualizer: Design Window
3. Visualizer: Design Exploration with the Advanced Search
4. Knowledge Check 1: Visualizer GUI
5. Visualizer: Source Code Debug
6. Visualizer: Variables Window
7. Visualizer: Adding Signals to the Wave Window
8. Knowledge Check 2: Visualizer GUI
9. Visualizer: Wave Window - Part 1
10. Visualizer: Wave Window - Part 2
11. Visualizer: Tracing Drivers and Receivers
12. Visualizer: X Tracing
13. Knowledge Check 3: Visualizer GUI
14. Visualizer: Memory Window
15. Visualizer: FSM Window
16. Knowledge Check 4: Visualizer GUI
17. Lab 3: Introduction to the Visualizer GUI
18. Assessment: Visualizer Graphical User Interface

5 Questa Working with Projects 9 Topics

1. Questa: What is a Project?
2. Questa: Creating a project in the GUI
3. Questa: Setting project properties
4. Knowledge Check 1: Questa Working with Projects
5. Questa: Using a Project in the GUI
6. Questa: Using The project Command
7. Knowledge Check 2: Questa Working with Projects
8. Lab 4: Questa Working with projects
9. Assessment: Questa Working with projects

6 Questa Mixed-HDL Designs 8 Topics

1. Questa: Mixed-HDL Design Considerations
2. Questa: Verilog inside VHDL
3. Questa: VHDL inside Verilog
4. Knowledge Check 1: Questa Mixed-HDL Designs
5. Questa: Accessing objects in a mixed Design
6. Knowledge Check 2: Questa Mixed-HDL Designs
7. Lab 5: Questa Mixed HDL Design
8. Assessment: Questa Mixed-HDL Designs

7 Questa Core HDL Simulation Exam 1 Topic

1. Level 1 Exam - Questa Core: HDL Simulation

Questa Core/Visualizer Advanced Topics 4  Chapters

This learning path enables you to extend your knowledge of QuestaSim functionality and debug HDL design using the Visualizer Debug Environment.

1 Code Coverage 17 Topics

1. Purpose and Benefits of Code Coverage
2. Types of Code Coverage
3. Enabling & Invoking Code Coverage
4. Knowledge Check 1: Questa Code Coverage
5. Coverage Windows in Visualizer Part 1
6. Coverage Windows in Visualizer Part 2
7. Testplan Analysis
8. Knowledge Check 2: Questa Code Coverage
9. Coverage Exclusion
10. Coverage Reports
11. Knowledge Check 3: Questa Code Coverage
12. Lab 1: Performing Code Coverage and Generating Coverage Reports
13. Managing Coverage
14. Merging Coverage Strategies
15. Knowledge Check 4: Questa Code Coverage
16. Lab 2: Merging UCDB
17. Assessment: Code Coverage

2 Profiler 18 Topics

1. Purpose of Using the Profiler
2. Profiler Flow
3. Profiler Engines - Usage Profiler
4. Knowledge Check 1: Profiler
5. Profiler Engines - Invoking Performance Profiler
6. Viewing Performance Profiler Results Part 1
7. Viewing Performance Profiler Results Part 2
8. Knowledge Check 2: Profiler
9. Profiler Engines - Solver Profiler
10. Knowledge Check 3: Profiler
11. Profiler Engines - Invoking Memory Profiler
12. Viewing Memory Profiler Results
13. Knowledge Check 4: Profiler
14. Compare Profiler Results
15. Profiler Reporting
16. Knowledge Check 5: Profiler
17. Lab 3: Analyzing Performance Using Visualizer Profiler
18. Assessment: Profiler

3 Controlling X-Propagation using xprop 6 Topics

1. xprop: Simulation with Xs
2. xprop Modes
3. xprop Usage
4. xprop Use Model
5. Lab 4: Controlling X-Propagation Using xprop
6. Assessment: Controlling X-Propagation Using xprop

4 Race Detection 5 Topics

1. Race Condition Overview
2. Race Detection Part 1
3. Race Detection Part 2
4. Lab 5: Detecting and Managing Simulation Races
5. Assessment: Race Detection

ModelSim / Questa Core Advanced Topics 6  Chapters

This learning path enables you to extend your knowledge of ModleSim/QuestaSim functionality and to efficiently analyze and debug HDL code.

1 ModelSim/Questa Tcl/TK Overview 10 Topics

1. ModelSim / Questa: Why Use Tcl/Tk?
2. ModelSim / Questa: Tcl Overview
3. ModelSim / Questa: Tcl Syntax
4. ModelSim / Questa: Using vsim Commands in Tcl Scripts
5. ModelSim / Questa: Simple Simulation Scripts
6. Knowledge Check 1: ModelSim/Questa - Tcl/Tk Overview
7. ModelSim / Questa: Tk Widgets and Custom GUI Buttons
8. Knowledge Check 2: ModelSim/Questa - Tcl/Tk Overview
9. Lab: ModelSim/Questa - Using Scripts and Tk Widgets in Simulation
10. Assessment: ModelSim/Questa - TCL/TK Overview

2 ModelSim/Questa Code Coverage 15 Topics

1. ModelSim / Questa: Purpose and Benefits of Code Coverage
2. ModelSim / Questa: Types of Code Coverage
3. Knowledge Check 1: ModelSim/Questa - Code Coverage
4. ModelSim / Questa: Invoking Code Coverage
5. ModelSim / Questa: Code Coverage Analysis Windows
6. Knowledge Check 2: ModelSim/Questa - Code Coverage
7. ModelSim / Questa: Managing Coverage Exclusions
8. ModelSim / Questasim: Reporting Coverage
9. Knowledge Check 3: ModelSim/Questa - Code Coverage
10. Lab: ModelSim/Questa - Performing Code Coverage
11. Modelsim / QuestaSim: Saving Coverage Data (UCDB)
12. ModelSim / Questa: Managing Coverage Data
13. Knowledge Check 4: ModelSim/Questa Code Coverage
14. Lab: ModelSim/Questa - Analyzing Code Coverage Results
15. Assessment: ModelSim/Questa - Code Coverage

3 ModelSim/Questa Language Support and Gate Level Simulations 13 Topics

1. ModelSim / Questa: SDF Annotation, VHDL and VHDL VITAL
2. ModelSim / Questa: VHDL Coding for Performance
3. Knowledge Check 1: ModelSim/Questa - Language Support
4. ModelSim / Questa: Verilog / SystemVerilog Version Support
5. ModelSim / Questa: How to Compile SV Files
6. ModelSim / Questa: Verilog Coding for Maximum Performance
7. Knowledge Check 2: ModelSim/Questa - Language Support
8. ModelSim / Questa: Verilog Delay Modes for Gate Level Simulations
9. ModelSim / Questa: Verilog SDF Timing Annotation
10. ModelSim / Questa: Verilog Gate Level Optimizations
11. Knowledge Check 3: ModelSim/Questa - Language Support
12. Lab: ModelSim/Questa - Gate Level Simulation
13. Assessment: ModelSim/Questa - Gate Level

4 ModelSim/Questa Finite State Machine Viewer 6 Topics

1. ModelSim/Questa: FSM Recognition
2. Knowledge Check 1: ModelSim/Questa FSM
3. ModelSim/Questa: Viewing FSM in GUI
4. Knowledge Check 2: ModelSim/Questa FSM
5. Lab: ModelSim/Questa Finite State Machine
6. Assessment: ModelSim/Questa FSM

5 ModelSim/Questa Selected Debugging Topics 18 Topics

1. ModelSim / Questa: Why Debug is Needed?
2. ModelSim / Questa: Checkpoint and Restore
3. ModelSim / Questa: Contention and Float Checking
4. ModelSim / Questa: Toggle and Stability Checking
5. ModelSim / Questa: Iteration Violations
6. Knowledge Check 1: ModelSim/Questa - Debugging
7. ModelSim / Questa: Post Simulation Analysis
8. ModelSim / Questa: IP Integrity
9. Lab: ModelSim / Quest - Iteration Limit
10. ModelSim / Questa: Hyperlinked Navigation
11. ModelSim / Questa: Tracing Readers and Drivers
12. Knowledge Check 2: ModelSim/Questa Debugging
13. ModelSim / Questa: Waveform Grouping
14. ModelSim / Questa: Saving Waveforms Between Cursors
15. ModelSim / Questa: Waveform Expanded Time
16. Knowledge Check 3: ModelSim/Questa - Debugging
17. Lab: ModelSim/Questa - Logic Error
18. Assessment: ModelSim/Questa - Debugging Topics

6 ModelSim/Questa Core: Advanced Topics Exam 1 Topic

1. Level 1 Certification - ModelSim/Questa Core: Advanced Topics

Mastering Questa 13  Chapters

This learning path helps you master Questa’s advanced functional verification environment in order to manage your tests and debug verification bugs.

1 Mastering Questa Learning Path Overview 1 Topic

1. Learning Path Overview

2 Verification Plan 15 Topics

1. Questa: Verification Motivations and Process
2. Questa: Verification Plan Components
3. Knowledge Check 1: Verification Plan
4. Questa: Verification Management Tasks
5. Questa: Unified Coverage Database (UCDB)
6. Knowledge Check 2: Verification Plan
7. Questa: Verification Management Flow
8. Questa: Creating a Verification Plan
9. Questa: Verification Plan Contents
10. Knowledge Check 3: Verification Plan
11. Questa: Export and Import a Verification Plan
12. Questa: Merging Verification Plan with Test Data
13. Knowledge Check 4: Verification Plan
14. Lab: The Verification Plan
15. Assessment: Verification Plan

3 Code Coverage 15 Topics

1. Questa: Purpose and Benefits of Code Coverage
2. Questa: Types of Code Coverage
3. Knowledge Check 1: Code Coverage
4. Questa: Invoking Code Coverage
5. Questa: Code Coverage Analysis Windows
6. Knowledge Check 2: Code Coverage
7. Questa: Managing Coverage Exclusions
8. Questa: Reporting Coverage
9. Knowledge Check 3: Code Coverage
10. Lab: Performing Code Coverage
11. Questa: Saving Coverage Data (UCDB)
12. Questa: Managing Coverage Data
13. Knowledge Check 4: Code Coverage
14. Lab: Analyzing Code Coverage Results
15. Assessment: Code Coverage

4 Functional Coverage 9 Topics

1. Questa: What is Functional Coverage?
2. Questa: How to Implement Functional Coverage?
3. Knowledge Check 1: Functional Coverage
4. Questa: Functional Coverage Plan
5. Questa: Filtering and Sampling Coverage
6. Questa: Functional Coverage in the GUI
7. Knowledge Check 2: Functional Verification
8. Lab: Functional Coverage
9. Assessment: Functional Coverage

5 Test Tracking 11 Topics

1. Questa: Creating a Test Environment
2. Questa: Storing Attributes in the UCDB
3. Questa: Coverage View Mode
4. Knowledge Check 1: Test Tracking
5. Questa: Post-Simulation Analysis
6. Questa: Optimizing Regression Runs
7. Questa: Verification Analysis
8. Questa: Generating HTML Coverage Reports
9. Knowledge Check 2: Test Tracking
10. Lab: Test Tracking
11. Assessment: Test Tracking

6 SV Class Debugging 23 Topics

1. Questa: Enabling Debugging for SV Classes
2. Questa: Questa Class Nomenclature
3. Questa: describe and examine Commands
4. Questa: Class Tree, Graph and Instances Windows
5. Knowledge Check 1: SV Class Debugging
6. Questa: Watch, Locals and Call Stack Windows
7. Questa: Viewing Class instances in the Wave Window
8. Questa: Finding Information about Your Classes
9. Knowledge Check 2: SV Class Debugging
10. Questa: User-Defined Radices
11. Questa: Memory Windows
12. Questa: Processes and Locals Windows
13. Knowledge Check 3: SV Class Debugging
14. Questa: Waveform Expanded Time
15. Questa: Tracing Readers and Drivers
16. Questa: Message Viewer window
17. Questa: Debugging Macros and the Call Command
18. Knowledge Check 4: SV Class Debugging
19. Questa: UVM-Aware Debug
20. Questa: Transaction Streams
21. Knowledge Check 5: SV Class Debugging
22. Lab: SystemVerilog Debugging
23. Assessment: SV Class Debugging

7 Performance 12 Topics

1. Questa: What is vopt?
2. Questa: Optimization Flows
3. Questa: Preserving Visibility
4. Questa: Optimization of Parameters and Generics
5. Questa: Preserving VPI/PLI Visibility
6. Knowledge Check 1: Performance
7. Questa: Gate Level Optimization
8. Questa: vopt with Compiled SDF
9. Questa: The PDU Flow
10. Knowledge Check 2: Performance
11. Lab: Performance
12. Assessment: Performance

8 Debugging SystemVerilog Assertions 11 Topics

1. Questa: Assertion-Based Verification
2. Questa: Assertions Window
3. Questa: Configure Assertions
4. Knowledge Check 1: Debugging SystemVerilog Assertions
5. Lab: Assertions Window
6. Questa: Assertions in the Wave Window
7. Questa: Assertion Thread Viewer Window
8. Questa: Usage of SV Bind Construct with Assertions
9. Knowledge Check 2: Debugging SystemVerilog Assertions
10. Lab: Debugging SystemVerilog Assertions
11. Assessment: Debugging SystemVerilog Assertions

9 Constrained Random Verification 7 Topics

1. Questa: Randomization
2. Questa: Constraint Random Coding Guidelines
3. Questa: Constraint Solvers
4. Questa: Debugging Randomization Failures
5. Knowledge Check 1: Constrained Random Verification
6. Lab: Debugging a Failure in the Constraint Solver
7. Assessment: Constrained Random Verification

10 Performance Profiling 7 Topics

1. Questa: Performance Profiling
2. Questa: Viewing Profiler Results
3. Knowledge Check 1: Performance Profiling
4. Questa: Memory Allocation Profiler
5. Questa: Capacity Analysis
6. Knowledge Check 2: Performance Profiling
7. Assessment: Performance Profiling

11 Transactions 6 Topics

1. Questa: What is a Transaction?
2. Questa: Transaction Recording Flow
3. Questa: Viewing Related Transactions in the Wave Window
4. Knowledge Check 1: Transactions
5. Lab: Transaction Recording and Viewing
6. Assessment: Transactions

12 Using DPI 9 Topics

1. Direct Programming Interface Introduction
2. Direct Programming Interface Importing C Routines
3. Direct Programming Interface Debugging with Questa
4. Lab: Introduction to DPI-C
5. Direct Programming Interface Models With Storage
6. Direct Programming Interface C Calling SystemVerilog
7. Knowledge Check: Using DPI
8. Lab: C Testbench
9. Assessment: Using DPI

13 Mastering Questa Exam 1 Topic

1. Level 1 Certification - Mastering Questa

Visualizer Debug Environment 6  Chapters

In this learning path you will learn how to use the Visualizer Debug Environment to verify your design.

1 Visualizer Learning Path Overview 1 Topic

1. Learning Path Overview

2 Chapter 1 - Introduction to Visualizer 5 Topics

1. Visualizer: What Is the Visualizer and Why Use It?
2. Visualizer: Typical Usage Flows
3. Visualizer: Getting Help
4. Lab 1: Introduction to Visualizer
5. Assessment Introduction to Visualizer

3 Chapter 2 - Visualizer GUI 18 Topics

1. Visualizer: Overview of GUI Operation
2. Visualizer: Design Window
3. Visualizer: Design Exploration with the Advanced Search
4. Knowledge Check 1: Visualizer GUI
5. Visualizer: Source Code Debug
6. Visualizer: Variables Window
7. Visualizer: Adding Signals to the Wave Window
8. Knowledge Check 2: Visualizer GUI
9. Visualizer: Wave Window - Part 1
10. Visualizer: Wave Window - Part 2
11. Visualizer: Tracing Drivers and Recievers
12. Visualizer: X Tracing
13. Knowledge Check 3: Visualizer GUI
14. Visualizer: Memory Window
15. Visualizer: FSM Window
16. Knowledge Check 4: Visualizer GUI
17. Lab 2: Visualizer GUI
18. Assessment: Visualizer GUI

4 Chapter 3 - Visualizer Commands 4 Topics

1. Visualizer: visualizer command
2. Visualizer: qwave2vcd and vcd2qwave Commands
3. Visualizer: Working with Waveforms
4. Assessment: Visualizer Commands

5 Chapter 4 - Debugging UVM Testbench 12 Topics

1. Visualizer: UVM Testbench Window
2. Visualizer: UVM Testbench in Schematic and Watch Windows
3. Visualizer: Class Debug
4. Knowledge Check 1: UVM Testbench
5. Lab 3: UVM Testbench Exploration
6. Visualizer: UVM Transactions Streams
7. Lab 4: UVM Transaction Streams
8. Visualizer: Assertions Window
9. Visualizer: Assertion Thread Viewer Window
10. Knowledge Check 2: UVM Testbench
11. Lab 5: Assertions
12. Assessment: Debugging UVM Testbench

6 Visualizer Debug Environment Exam - v22.18.01 1 Topic

1. Level 1 Exam - Visualizer

Visualizer Advanced 1  Chapter

In this learning path you will learn to use the Visualizer Debug Environment to analyze coverage results obtained from Questa simulation.

1 Visualizer: Coverage Analysis 7 Topics

1. Visualizer: Exploring Coverage
2. Visualizer: Coverage Metrics for Design Hierarchy
3. Visualizer: Analyzing Code Coverage
4. Visualizer: Test Analysis and Ranking Tests
5. Visualizer: Coverage Exclusions
6. Visualizer: Coverage Reports and Modified UCDB Files
7. Assessment: Coverage Analysis

Questa SIM SystemC 2  Chapters

In this learning path you will receive an overview of SystemC and learn how to simulate SystemC designs in Questa.

1 Introduction to SystemC 10 Topics

1. Questa SIM SystemC: Introduction to C++
2. Questa SIM SystemC: Introduction to SystemC
3. Questa SIM SystemC: SystemC Basic Contructs
4. Knowledge Check 1: Introduction to SystemC
5. Questa SIM SystemC: SystemC Design Hierarchy
6. Questa SIM SystemC: SystemC Data Types
7. Questa SIM SystemC: SystemC Time
8. Knowledge Check 2: Introduction to SystemC
9. Lab 1: SystemC Hello World
10. Assessment: Introduction to SystemC

2 SystemC in Questa SIM 6 Topics

1. Questa SIM SystemC: Questa SIM SystemC General Flow
2. Questa SIM SystemC: Mixed HDL Support
3. Questa SIM SystemC: SystemC Different Flows
4. Lab 2: SystemC Shared Library Flow
5. Lab 3: SystemC Archived Models
6. Assessment: SystemC in Questa SIM

Questa Clock Domain Crossing (CDC) 2  Chapters

Learn about clock domain crossing (CDC) design and verification and how to use Questa CDC to verify paths between asynchronous clock domains.

1 Basic CDC Verification 25 Topics

1. Questa CDC Introduction: CDC Challenges
2. Questa CDC Introduction: CDC Verification
3. Questa CDC: CDC Methodology - Part 1
4. Questa CDC: CDC Methodology - Part 2
5. Questa CDC: CDC Methodology - Part 3
6. Knowledge Check 1: CDC Overview
7. Questa CDC Setup: Understanding CDC Process and Design Compilation
8. Questa CDC Setup: Tcl Commands
9. Knowledge Check 2: CDC Overview
10. Questa CDC Setup: Clock Report
11. Questa CDC Setup: Clock Signals and Clock Grouping
12. Knowledge Check 3: CDC Overview
13. Questa CDC Setup: Resets and Port Domains
14. Knowledge Check 4: CDC Overview
15. Questa CDC Debug
16. Questa CDC: Synchronizer Flows for DFF, DMUX and Handshake Schemes
17. Questa CDC: Synchronizer Flow for FIFO Schemes
18. Knowledge Check 5: CDC Overview
19. Questa CDC: Reconvergence Schemes and Synchronizer Reporting
20. Knowledge Check 6: CDC Overview
21. Questa CDC: Status Method - Part 1
22. Questa CDC: Status Method - Part 2
23. Questa CDC: Status Method - Part 3
24. Knowledge Check 7: CDC Overview
25. Assessment: CDC Overview

Questa® Lint 2  Chapters

Learn how to use Questa® Lint to perform a fast check of your HDL RTL looking for completeness and consistency issues.

1 Chapter 1 - Introduction to Questa Lint 11 Topics

1. Questa Lint: Overview of Workflow
2. Questa Lint: Methodologies and Checks
3. Questa Lint: Running Analysis in Batch
4. Questa Lint: Running Analysis in the GUI
5. Knowledge Check 1: Introduction to Questa Lint
6. Lab 1: Run Questa Lint Analysis in Batch & Lab 2: Run Questa Lint Analysis in GUI
7. Questa Lint: Generated Reports
8. Questa Lint: Managing Results in the GUI
9. Knowledge Check 2: Introduction to Questa Lint
10. Lab 3: View Results in GUI
11. Assessment: Introduction to Questa Lint

2 Chapter 2 - Questa Lint Additional Feature 9 Topics

1. Questa Lint: Working with Waiver file
2. Questa Lint: Dashboard View & Lint Quality Score
3. Questa Lint: Working with Schematics
4. Knowledge Check 1: Questa Lint Additional Features
5. Questa Lint: Working with Custom Goals
6. Questa Lint: Incremental Analysis
7. Knowledge Check 2: Questa Lint Additional Features
8. Lab 4: Working with Custom Goals
9. Assessment: Questa Lint Additional Features

HDS: Basic Operation 6  Chapters

This learning path covers the core operations of HDL Designer (HDS), use of the Block Diagram, and State Machine editors and how to control simulations from HDS

1 HDS: HDL Designer Basics 23 Topics

1. HDS: What is HDL Designer?
2. HDS: Getting Help
3. Knowledge Check 1: HDS - Basics
4. HDS: Design Manager Basics
5. HDS: Initial Configuration of HDS
6. HDS: Project Manager Contents
7. HDS: Creating and Opening Projects in HDS
8. Knowledge Check 2: HDS - Basics
9. HDS: Creating Libraries and What They Contain
10. Lab: HDS Project and Library
11. HDS: Introduction to Design Explorer in Design Unit mode
12. HDS: Using the Hierarchy Pane in Design Explorer
13. Knowledge Check 3: HDS - Basics
14. HDS: Copying Design Units and Views in the Design Explorer
15. HDS: Introduction to Design Explorer in File Browser Mode
16. HDS: Introduction to Design Explorer in Logical Object Mode
17. Knowledge Check 4: HDS - Basics
18. HDS: How to Use the Design Explorer Side Data Windows
19. HDS: How to Use the Design Explorer Downstream Windows
20. HDS: How to Use the Design Explorer Task and Template Windows
21. Knowledge Check 5: HDS - Basics
22. Lab: HDS Introduction to Design Explorer
23. Assessment: HDS Basics

2 HDS: Design Entry Common Features 15 Topics

1. HDS: Opening New or Existing Design Units
2. HDS: Bottom Up Design Flow
3. HDS: Top Down Design Flow
4. HDS: How to Save the Design
5. Knowledge Check 1: HDS Common Features
6. Lab: HDS Opening and Closing Designs
7. HDS: Adding Comments to Design Entry Tools
8. HDS: Defining the Page Setup for Viewing and Printing
9. HDS: Setting Package Preferences
10. HDS: Setting Preferences for the Design Tools
11. HDS: Using the Diagram Browser
12. HDS: How to Generate HDL Code from Graphics
13. Knowledge Check 2: HDS Common Features
14. Lab: HDS Preferences
15. Assessment: HDS Common Features

3 HDS: Block Diagrams 24 Topics

1. HDS: Definition and Use of Block Diagrams
2. HDS: Adding Blocks and Components
3. HDS: Adding ModuleWare
4. Lab: HDS Adding Blocks and Components
5. HDS: Adding Connections to Block Diagrams
6. HDS: Connecting Blocks and Components
7. HDS: Adding Ports to Block Diagrams
8. HDS: Auto and Interactive Routing
9. Knowledge Check 1: HDS Block Diagram
10. HDS: Setting Block and Component Properties
11. HDS: Promoting Blocks to Components
12. HDS: Setting Signal and Port Properties
13. HDS: User Declarations and Visibility
14. Knowledge Check 2: HDS Block Diagram
15. Lab: HDS Connecting Up Block Diagrams
16. HDS: Navigating Through Block Diagram Hierarchy
17. HDS: Reconciling Interfaces
18. HDS: Highlighting Nets Through Hierarchy
19. HDS: Changing Hierarchical Nets
20. HDS: Adding and Removing Hierarchy from Block Diagrams
21. HDS: Looking at Block Diagrams as IBDs
22. HDS Block Diagram Knowledge Check 3
23. Lab: HDS: Manipulating Block Diagrams
24. Assessment: HDS Block Diagram

4 HDS: State Machine Creation 17 Topics

1. HDS: State Machine Objects and How to Add Them
2. HDS: Adding and Removing Hierarchy to the State Diagram
3. HDS: Using Wait States
4. Knowledge Check 1: HDS State Machine Creation
5. HDS: Making State Assignments
6. Lab: HDS: Adding Objects to State Diagrams
7. HDS: Transition Conditions and Assignments
8. HDS: Output Assignment Priority
9. HDS: Implementing Moore and/or Mealy State Machines
10. HDS: Defining Clock, Reset and Enable
11. Knowledge Check 2: HDS State Machine Creation
12. Lab: HDS: Adding Transitions to State Diagrams
13. HDS: Using Concurrent State Machines
14. HDS: The Expression Builder
15. Knowledge Check 3: HDS State Machine Creation
16. Lab: HDS: Concurrent State Diagrams
17. Assessment: HDS: State Machine Creation

5 HDS: State Machine Code Generation 12 Topics

1. HDS: Common State Machine HDL Styles
2. HDS: Using Output Default Values
3. HDS: Timing Differences between Output Signal Types Part 1
4. HDS: Timing Differences between Output Signal Types Part 2
5. HDS: Adding Declarations and Statements to the State Machine Code
6. Knowledge Check 1: HDS: State Machine Code Generation
7. HDS: Defining the Format of State Machine HDL
8. HDS: Defining State Encoding for Synthesis
9. HDS: Analyzing Signals Table
10. Knowledge Check 2: HDS: State Machine Code Generation
11. Lab: HDS Generating State Machine HDL Code
12. Assessment: HDS State Machine Code Generation

6 HDS: Simulating and Debugging Designs Within HDS 17 Topics

1. HDS: Creating a Top Level Testbench in HDL Designer
2. HDS: Describing Tester Operation in HDL Designer
3. Knowledge Check 1: HDS: Simulating and Debugging Designs Within HDS
4. Lab: HDS: Creation of a Testbench
5. HDS: Setting Up the Chosen Simulator
6. HDS: Starting the Simulation
7. HDS: Solving Compile and Elaboration Errors
8. Knowledge Check 2: HDS: Simulating and Debugging Designs Within HDS
9. Lab: HDS: Compiling and Entering the Simulator
10. HDS: Running the Simulation from HDS Windows
11. HDS: Setting Breakpoints from HDS Windows
12. HDS: Animating HDS Windows During Simulation
13. HDS: Reviewing Animation History
14. HDS: How to Enable Code Coverage Collection in Simulator
15. Knowledge Check 3: HDS: Simulating and Debugging Designs Within HDS
16. Lab: HDS: Simulation Control and Animation
17. Assessment: HDS: Simulating and Debugging Designs Within HDS

HDS: Team Use and File Management 6  Chapters

This learning path covers how to administer HDS for team operation, how to analyze existing designs, how to generate documentation, and how to use 3rd party IP.

1 HDS: Using Viewpoints to Aid Investigation and Understanding of Designs 9 Topics

1. HDS: Visualizing Design Data with Viewpoints
2. HDS: Setting the Columns seen in Design Explorer Views
3. HDS: Obtaining Summary Information on Your Design
4. Knowledge Check 1: HDS - Using Viewpoints to Aid Investigation and Understanding of Designs
5. HDS: Using the Advanced Find in Design Explorer
6. HDS: Using the Available Design Reports
7. Knowledge Check 2: HDS - Using Viewpoints to Aid Investigation and Understanding of Designs
8. Lab: HDS - Using Viewpoints to Aid Investigation and Understanding of Designs
9. Assessment: HDS - Using Viewpoints to Aid Investigation and Understanding of Designs

2 HDS: Setting up HDS Properties and Resources 8 Topics

1. HDS: Defining the Available Resources
2. HDS: Declaring User Variables
3. Knowledge Check 1: HDS - Setting up HDS Properties and Resources
4. HDS: Defining Default Code Generation Preferences
5. HDS: User Defined Templates
6. Knowledge Check 2: HDS - Setting up HDS Properties and Resources
7. Lab: HDS - Setting up HDS Properties and Resources
8. Assessment: HDS - Setting up HDS Properties and Resources

3 HDS: IP and Vendor Flows 17 Topics

1. HDS: How to Use IP Blocks within HDL Designer Designs
2. HDS: ModuleWare IP
3. HDS: Setting ModuleWare Instance Properties in Block Diagrams
4. Knowledge Check 1: HDS - IP and Vendor Flows
5. Lab: HDS ModuleWare Lab
6. HDS: Introduction to Using Vendor IP Flows
7. HDS: Xilinx CoreGen Flow
8. HDS: Xilinx Vivado Flow
9. HDS: Xilinx Vivado Flow Example
10. HDS: Altera MegaWizard Flow
11. Knowledge Check 2: HDS - IP and Vendor Flows
12. Lab: HDS Vendor Lab
13. HDS: How to Add a Gate Level Netlist into HDS
14. HDS: Verifying Gate Level Simulation Results
15. Knowledge Check 3: HDS - IP and Vendor Flows
16. Lab: HDS Gate Level Lab
17. Assessment: HDS - IP and Vendor Flows

4 HDS: Adding and Visualizing Existing Designs 9 Topics

1. HDS: Design Reuse Part 1
2. HDS: Design Reuse Part 2
3. Knowledge Check 1: HDS - Adding and Visualizing Existing Designs
4. HDS: Visualization Versus Entry
5. HDS: Visualizing a Text File
6. HDS: Converting a Visualized File to a Graphics File
7. Knowledge Check 2: HDS - Adding and Visualizing Existing Designs
8. Lab: HDS - Adding and Visualizing Existing Designs
9. Assessment: HDS - Adding and Visualizing Existing Designs

5 HDS: Introduction to Team Design 9 Topics

1. HDS: Team Requirements
2. HDS: Defining Team Resources
3. Knowledge Check 1: HDS - Introduction to Team Design
4. HDS: Differences Between Team and User Preferences
5. HDS: Differences Between Team and User Templates and Tasks
6. HDS: Setting Team Version Management
7. Knowledge Check 2: HDS - Introduction to Team Design
8. Lab: HDS - Introduction to Team Design
9. Assessment: HDS - Introduction to Team Design

6 HDS: Producing Design Documentation 11 Topics

1. HDS: Advantages and Limitations of OLE to Export Diagrams
2. HDS: OLE When Using the Drag Bar and Panels
3. HDS: How to Register and Use OLE Documentation Tools
4. HDS: Documenting Diagrams without OLE
5. Knowledge Check 1: HDS - Producing Design Documentation
6. Lab: HDS - Creating Documentation
7. HDS: Invoking HTML Creation
8. HDS: HTML Options and Settings Explained
9. Knowledge Check 2: HDS - Producing Design Documentation
10. Lab: HDS - Producing Design Documentation
11. Assessment: HDS - Producing Design Documentation

HDS: Design Checker 4  Chapters

This learning path supports users writing rtl code. It helps them implement their company design guidelines as a rule set that can be tested by Design Checker.

1 HDS: Introduction to DesignChecker 8 Topics

1. HDS: Introducing Static Design Checking
2. HDS: Overview of DesignCheck Process
3. Knowledge Check 1: HDS - Introduction to DesignChecker
4. HDS: Overview of Running DesignChecker
5. HDS: DesignChecker Windows
6. Knowledge Check 2: HDS - Introduction to DesignChecker
7. Lab: HDS - Introduction to DesignChecker
8. Assessment: HDS - Introduction to DesignChecker

2 HDS: Understanding Rulesets and Policies 13 Topics

1. HDS: Base Rules
2. HDS: Base Rule Parameters and Reference Guide
3. Knowledge Check 1: HDS - Understanding Rulesets and Policies
4. HDS: Building a Ruleset
5. HDS: Built-in Rulesets
6. HDS: Design Quality Metric
7. Knowledge Check 2: HDS - Understanding Rulesets and Policies
8. Lab: HDS - DC Ruleset Creation
9. HDS: Creating a Policy
10. HDS: Using Policies
11. Knowledge Check 3: HDS - Understanding Rulesets and Policies
12. Lab: HDS - DC Policy Creation
13. Assessment: HDS - Understanding Rulesets and Policies

3 HDS: Invoking and using DesignChecker in HDS 6 Topics

1. HDS: How to See DesignChecker in HDS
2. Knowledge Check 1: HDS - Invoking and using DesignChecker in HDS
3. HDS: Invoking DesignChecker from HDS
4. Knowledge Check 2: HDS - Invoking and using DesignChecker in HDS
5. Lab: HDS - Invoking and using DesignChecker in HDS
6. Assessment: HDS - Invoking and using DesignChecker in HDS

4 HDS: Analyzing DesignChecker Results 12 Topics

1. HDS: The Results Tab
2. HDS: Results Summary Pane
3. HDS: Tracing Errors to Design Source Views
4. Knowledge Check 1: HDS - Analyzing DesignChecker Results
5. Lab: HDS - Analyzing Results
6. HDS: How to Sort and Filter Results
7. HDS: Exporting of Results
8. HDS: Using DC to Analyze Quality of a Design
9. Knowledge Check 2: HDS - Analyzing DesignChecker Results
10. Lab: HDS - Exporting and Organizing Results
11. Lab: HDS - Working with Results
12. Assessment: HDS - Analyzing DesignChecker Results

SystemVerilog Fundamentals 8  Chapters

In this learning path you will learn SystemVerilog fundamentals such as blocks, data types, and operators.

1 SystemVerilog Concepts 12 Topics

1. SystemVerilog Verification Introduction
2. SystemVerilog Random Verification
3. SystemVerilog Coverage
4. SystemVerilog Levels of Abstraction
5. Knowledge Check 1: SystemVerilog Concepts
6. SystemVerilog Compiler Directives
7. SystemVerilog Time and Delays
8. SystemVerilog System Tasks and Functions
9. SystemVerilog Testbench Organization
10. Knowledge Check 2: SystemVerilog Concepts
11. Lab: Simulate and Debug a 1-bit Adder
12. Assessment: SystemVerilog Concepts

2 SystemVerilog Integral Data Types 16 Topics

1. SystemVerilog Syntax
2. SystemVerilog Literals
3. SystemVerilog Data Types and Value Sets
4. SystemVerilog Vectors
5. Knowledge Check 1: SystemVerilog Integral Data Types
6. SystemVerilog Enumerated Types
7. SystemVerilog User Defined Types
8. SystemVerilog Casting
9. Knowledge Check 2: SystemVerilog Integral Data Types
10. SystemVerilog Hierarchical References
11. SystemVerilog Port Declaration
12. SystemVerilog Port Connections
13. SystemVerilog Parameters and Constants
14. Knowledge Check 3: SystemVerilog Integral Data Types
15. Lab: Using 4-State and 2-State Types
16. Assessment: SystemVerilog Integral Data Types

3 SystemVerilog Procedural Blocks and Routines 12 Topics

1. SystemVerilog Event Simulation
2. SystemVerilog Initial and Always Blocks
3. SystemVerilog Blocking and Non-blocking Assignment Statements
4. SystemVerilog Continuous Assignment Statements
5. Knowledge Check 1: SystemVerilog Procedural Blocks and Routines
6. SystemVerilog Tasks and Functions
7. SystemVerilog Routine Arguments
8. SystemVerilog Routine Storage
9. SystemVerilog Ref Arguments and Defaults
10. Knowledge Check 2: SystemVerilog Procedural Blocks and Routines
11. Lab: Model and Verify a Johnson Counter
12. Assessment: SystemVerilog Procedural Blocks and Routines

4 SystemVerilog Programming Statements 9 Topics

1. SystemVerilog If and Assert Statements
2. SystemVerilog Case Statements
3. Knowledge Check 1: SystemVerilog Programming Statements
4. SystemVerilog Forever, Repeat, and While Loops
5. SystemVerilog For-loop and Foreach-loop
6. SystemVerilog Labels and the Disable, Continue, and Break Statements
7. Knowledge Check 2: SystemVerilog Programming Statements
8. Lab: Model and Verify a BCD Encoder
9. Assessment: SystemVerilog Programming Statements

5 SystemVerilog Operators 15 Topics

1. SystemVerilog Operators Introduction
2. SystemVerilog Bitwise and Unary-Reduction Operators
3. SystemVerilog Logical and Comparison Operators
4. SystemVerilog Equality Operators
5. SystemVerilog Inside Operator
6. Knowledge Check 1: SystemVerilog Operators
7. SystemVerilog Shift and Concatenate Operators
8. SystemVerilog Conditional Operator
9. SystemVerilog Arithmetic Operators
10. SystemVerilog Streaming Operators
11. SystemVerilog Assignment Operators
12. SystemVerilog Operation Size
13. Knowledge Check 2: SystemVerilog Operators
14. Lab: Model and Verify an ALU
15. Assessment: SystemVerilog Operators

6 SystemVerilog Arrays, Structures, and Packages 18 Topics

1. SystemVerilog - Vectors and Arrays
2. SystemVerilog Array - Assignment and Comparison
3. SystemVerilog - Array Literals
4. Knowledge Check 1: SystemVerilog Arrays, Structures, and Packages
5. SystemVerilog - Dynamic Arrays
6. SystemVerilog - Strings
7. SystemVerilog - Queues
8. Knowledge Check 2: SystemVerilog Arrays, Structures, and Packages
9. SystemVerilog - Associative Arrays
10. SystemVerilog - Array Methods
11. SystemVerilog - Advanced Array Methods
12. Knowledge Check 3: SystemVerilog Arrays, Structures, and Packages
13. SystemVerilog - Structures
14. SystemVerilog - Packages
15. SystemVerilog - Package Import
16. Knowledge Check 4: SystemVerilog Arrays, Structures, and Packages
17. Lab: SystemVerilog Arrays, Structures, and Packages
18. Assessment: SystemVerilog Arrays, Structures, and Packages

7 SystemVerilog Interfaces 9 Topics

1. SystemVerilog - Ports and Interfaces
2. SystemVerilog Interface - Signals, Methods and Ports
3. SystemVerilog - Modports
4. Knowledge Check 1: SystemVerilog Interfaces
5. SystemVerilog - Parameterized Interfaces
6. SystemVerilog - Connecting with Interfaces
7. Knowledge Check 2: SystemVerilog Interfaces
8. Lab: Create an Inter-processor Interface
9. Assessment: SystemVerilog Interfaces

8 SystemVerilog Verification Constructs 10 Topics

1. SystemVerilog - Final Block
2. SystemVerilog - Fork-Join Introduction
3. SystemVerilog - Fork-Join Flavors
4. Knowledge Check 1: SystemVerilog Verification Constructs
5. SystemVerilog - Force and Release
6. SystemVerilog - Reading Memory Files
7. SystemVerilog - File I/O
8. Knowledge Check 2: SystemVerilog Verification Constructs
9. Lab: Verify with Testbench Interfaces
10. Assessment: SystemVerilog Verification Constructs

SystemVerilog OOP and IPC 3  Chapters

In this learning path you will learn SystemVerilog Object Oriented Programming and Inter-Process Communication.

1 SystemVerilog Basic OOP 17 Topics

1. SystemVerilog Introduction to Object Oriented Programming
2. SystemVerilog Introduction to Classes
3. SystemVerilog Questa Sim OOP Debug
4. SystemVerilog Constructors
5. Knowledge Check 1: SystemVerilog Basic OOP
6. SystemVerilog Handles and Objects 1
7. SystemVerilog Handles and Objects 2
8. SystemVerilog Shallow Object Copy
9. SystemVerilog Deep Object Copy
10. SystemVerilog Cloning Objects
11. Knowledge Check 2: SystemVerilog Basic OOP
12. SystemVerilog Class Declaration Details
13. SystemVerilog Static Properties and Methods
14. SystemVerilog Virtual Interfaces
15. Knowledge Check 3: SystemVerilog Basic OOP
16. Lab: SystemVerilog Basic OOP
17. Assessment: SystemVerilog Basic OOP

2 SystemVerilog Advanced OOP 15 Topics

1. SystemVerilog Class Extension
2. SystemVerilog Advanced OOP Terminology
3. SystemVerilog Transaction Generator
4. Knowledge Check 1: SystemVerilog Advanced OOP
5. SystemVerilog Handles and Objects 3
6. SystemVerilog Virtual Methods
7. SystemVerilog Virtual Method Prototype
8. Knowledge Check 2: SystemVerilog Advanced OOP
9. SystemVerilog Generator and Virtual Methods
10. SystemVerilog Advanced Constructors
11. SystemVerilog Parameterized Classes
12. SystemVerilog Class Member Visibility
13. Knowledge Check 3: SystemVerilog Advanced OOP
14. Lab: SystemVerilog Advanced OOP
15. Assessment: SystemVerilog Advanced OOP

3 SystemVerilog Interprocess Communication 9 Topics

1. SystemVerilog Introduction to Interprocess Communication
2. SystemVerilog Fork-Join
3. SystemVerilog Fork-Join_none
4. SystemVerilog Fork-Join_any
5. Knowledge Check 1: SystemVerilog Interprocess Communication
6. SystemVerilog Disable Threads
7. SystemVerilog Spawning Threads in a Loop
8. Knowledge Check 2: SystemVerilog Interprocess Communication
9. Assessment: SystemVerilog Interprocess Communication

SystemVerilog Randomization and Functional Coverage 2  Chapters

In this learning path you will learn about SystemVerilog Constrained Random Generation and Functional Coverage.

1 SystemVerilog Randomization 19 Topics

1. SystemVerilog Class-Based Randomization
2. SystemVerilog Randomization Example
3. SystemVerilog Constraint Solver
4. SystemVerilog Membership, Distribution, and Unique Constraints
5. SystemVerilog Implication Constraint
6. Knowledge Check 1: SystemVerilog Randomization
7. SystemVerilog Randomizing Arrays
8. SystemVerilog Randomizing Aggregate Types
9. SystemVerilog Random Distribution and Probability
10. SystemVerilog Constraint Inheritance and In-Line Constraints
11. SystemVerilog Soft Constraints
12. Knowledge Check 2: SystemVerilog Randomization
13. SystemVerilog Randomization Setup and Cleanup
14. SystemVerilog Random Cyclic Variables
15. SystemVerilog Disabling Randomization
16. SystemVerilog Randomization Issues and Alternatives
17. Knowledge Check 3: SystemVerilog Randomization
18. Lab: SystemVerilog Randomization
19. Assessment: SystemVerilog Randomization

2 SystemVerilog Functional Coverage 17 Topics

1. SystemVerilog Coverage Comparison
2. SystemVerilog Functional Coverage Strategies
3. SystemVerilog Functional Coverage Flow
4. Knowledge Check 1: SystemVerilog Functional Coverage
5. SystemVerilog Covergroup Definition
6. SystemVerilog Sampling and Conditional Coverage
7. SystemVerilog Coverpoint Bins
8. SystemVerilog Special Coverage Bins
9. Knowledge Check 2: SystemVerilog Functional Coverage
10. SystemVerilog Cross Coverage
11. SystemVerilog Generic Covergroups
12. SystemVerilog Coverage Options
13. SystemVerilog Coverage Methods
14. SystemVerilog Transition Coverage
15. Knowledge Check 3: SystemVerilog Functional Coverage
16. Lab: SystemVerilog Functional Coverage
17. Assessment: SystemVerilog Functional Coverage

Functional Safety 2  Chapters

Students will learn the basics of functional safety and how to run the Siemens tools to measure safety metrics for their designs.

1 Introduction 9 Topics

1. Functional Safety Overview
2. ISO-26262 Overview
3. Safety Analysis
4. Knowledge Check 1: Introduction
5. Failure Mode Types
6. Safety Metrics
7. FuSa Tool Flow
8. Knowledge Check 2: Introduction
9. Assessment: Introduction

2 Analysis 9 Topics

1. Safety Analysis Introduction
2. Diagnostic Coverage
3. Safety Mechanisms
4. Knowledge Check 1: Analysis
5. Running SafetyScope
6. SafetyScope Output and Debug
7. Knowledge Check 2: Analysis
8. Lab: SafetyScope Analysis and Exploration
9. Assessment: Analysis

Questa Formal Verification 6  Chapters

You will learn how to set up your design in Questa Formal software and how to use AutoCheck, XCheck, CoverCheck and PropCheck to debug and verify your design.

1 Questa Formal Compilation and Directives 2 Topics

1. Questa Formal Common Directives
2. Questa Formal Compile Library

2 Questa Formal Clocking and Initialization 2 Topics

1. Questa Formal Initialization
2. Questa Formal Clocking

3 Questa Formal AutoCheck 2 Topics

1. AutoCheck -Level 1
2. AutoCheck -Level 2

4 Questa Formal CoverCheck 2 Topics

1. CoverCheck Level 1
2. CoverCheck Level 2

5 Questa Formal X-Check 2 Topics

1. X-Check Level 1
2. X-Check Level 2

6 Questa Formal PropCheck 1 Topic

1. PropCheck Level 1

SystemVerilog for Verification Recordings 12  Chapters

Learn about SystemVerilog constructs, object oriented programming, constrained random testing, and functional coverage with live recordings, labs, & quizzes.

1 SystemVerilog Concepts and Guidelines 5 Topics

1. SystemVerilog Concepts and Guidelines
2. Knowledge Check 1: SystemVerilog Concepts and Guidelines
3. Knowledge Check 2: SystemVerilog Concepts and Guidelines
4. Lab: SystemVerilog Simulate and Debug a 1-bit Adder
5. Assessment: SystemVerilog Concepts and Guidelines

2 SystemVerilog Syntax and Data Types 7 Topics

1. SystemVerilog Syntax
2. SystemVerilog Data Types
3. Knowledge Check 1: SystemVerilog Syntax and Data Types
4. Knowledge Check 2: SystemVerilog Syntax and Data Types
5. Knowledge Check 3: SystemVerilog Syntax and Data Types
6. Lab: SystemVerilog Using 4-State and 2-State Types
7. Assessment: SystemVerilog Syntax and Data Types

3 SystemVerilog Procedural Blocks and Statements 5 Topics

1. SystemVerilog Procedural Blocks and Statements
2. Knowledge Check 1: SystemVerilog Procedural Blocks and Statements
3. Knowledge Check 2: SystemVerilog Procedural Blocks and Statements
4. Lab: SystemVerilog Model and Verify a Johnson Counter
5. Assessment: SystemVerilog Procedural Blocks and Statements

4 SystemVerilog Programming Statements 5 Topics

1. SystemVerilog Programming Statements
2. Knowledge Check 1: SystemVerilog Programming Statements
3. Knowledge Check 2: SystemVerilog Programming Statements
4. Lab: SystemVerilog Model and Verify a BCD Encoder
5. Assessment: SystemVerilog Programming Statements

5 SystemVerilog Operators and Operation Rules 5 Topics

1. SystemVerilog Operators and Operation Rules
2. Knowledge Check 1: SystemVerilog Operators
3. Knowledge Check 2: SystemVerilog Operators
4. Lab: SystemVerilog Model and Verify an ALU
5. Assessment: SystemVerilog Operators

6 SystemVerilog Arrays and Packages 8 Topics

1. SystemVerilog Arrays
2. Knowledge Check 1: SystemVerilog Arrays and Packages
3. Knowledge Check 2: SystemVerilog Arrays and Packages
4. Knowledge Check 3: SystemVerilog Arrays and Packages
5. SystemVerilog Packages
6. Knowledge Check 4: SystemVerilog Arrays and Packages
7. Lab: SystemVerilog Arrays and Packages
8. Assessment: SystemVerilog Arrays and Packages

7 SystemVerilog Interfaces and Ports 5 Topics

1. SystemVerilog Interfaces and Ports
2. Knowledge Check 1: SystemVerilog Interfaces
3. Knowledge Check 2: SystemVerilog Interfaces
4. Lab: Verify With Testbench Interfaces
5. Assessment: SystemVerilog Interfaces

8 SystemVerilog Basic OOP 8 Topics

1. SystemVerilog Introduction to Object Oriented Programming
2. Knowledge Check 1: SystemVerilog Basic OOP
3. SystemVerilog Copy and Clone
4. Knowledge Check 2: SystemVerilog Basic OOP
5. SystemVerilog Virtual Interface
6. Knowledge Check 3: SystemVerilog Basic OOP
7. Lab: SystemVerilog Basic OOP
8. Assessment: SystemVerilog Basic OOP

9 SystemVerilog Advanced OOP 8 Topics

1. SystemVerilog Class Extension
2. Knowledge Check 1: SystemVerilog Advanced OOP
3. SystemVerilog Polymorphism
4. Knowledge Check 2: SystemVerilog Advanced OOP
5. SystemVerilog Parameterized Classes
6. Knowledge Check 3: SystemVerilog Advanced OOP
7. Lab: SystemVerilog Advanced OOP
8. Assessment: SystemVerilog Advanced OOP

10 SystemVerilog Constrained Random Generation 7 Topics

1. SystemVerilog Class-Based Randomization
2. Knowledge Check 1: SystemVerilog Constrained Random Generation
3. SystemVerilog Randomization and Inheritance
4. Knowledge Check 2: SystemVerilog Constrained Random Generation
5. Knowledge Check 3: SystemVerilog Constrained Random Generation
6. Lab: SystemVerilog Constrained Randomization
7. Assessment: SystemVerilog Constrained Random Generation

11 SystemVerilog Functional Coverage 6 Topics

1. SystemVerilog Functional Coverage
2. Knowledge Check 1: SystemVerilog Functional Coverage
3. Knowledge Check 2: SystemVerilog Functional Coverage
4. Knowledge Check 3: SystemVerilog Functional Coverage
5. Lab: SystemVerilog Functional Coverage
6. Assessment: SystemVerilog Functional Coverage

12 SystemVerilog Threads and Interprocess Communication 6 Topics

1. SystemVerilog Threads and Interprocess Communication
2. Knowledge Check 1: SystemVerilog Threads and Interprocess Communication
3. Knowledge Check 2: SystemVerilog Threads and Interprocess Communication
4. Knowledge Check 3: SystemVerilog Threads and Interprocess Communication
5. Lab: SystemVerilog Threads and Interprocess Communication
6. Assessment: SystemVerilog Threads and Interprocess Communication

SystemVerilog UVM Recordings 10  Chapters

Learn how to use the Universal Verification Methodology (UVM) to create reusable verification environments by watching live recordings.

1 UVM Overview 9 Topics

1. UVM Methodology
2. Knowledge Check 1: UVM Overview
3. UVM Example
4. Knowledge Check 2: UVM Overview
5. Knowledge Check 3: UVM Overview
6. UVM Factory and Messaging
7. Knowledge Check 4: UVM Overview
8. Lab: First Look at SystemVerilog UVM
9. Assessment: UVM Overview

2 UVM Transactions and Sequences 6 Topics

1. UVM Transactions and Sequences
2. Knowledge Check 1: UVM Transactions and Sequences
3. Knowledge Check 2: UVM Transactions and Sequences
4. Knowledge Check 3: UVM Transactions and Sequences
5. Lab: UVM Transactions and Sequences
6. Assessment: UVM Transactions and Sequences

3 UVM Drivers and Sequencers 4 Topics

1. UVM Drivers, Sequencers, and TLM
2. Knowledge Check 1: UVM Drivers and Sequencers
3. Lab: UVM Sequencers and Drivers
4. Assessment: UVM Drivers and Sequencers

4 UVM Monitors and Agents 4 Topics

1. UVM Monitors and Agents
2. Knowledge Check: UVM Monitors and Agents
3. Lab: UVM Monitors and Agents
4. Assessment: UVM Monitors and Agents

5 UVM Coverage Collectors 4 Topics

1. UVM Coverage Collectors
2. Knowledge Check: UVM Coverage Collectors
3. Lab: UVM Coverage Collector
4. Assessment: UVM Coverage Collectors

6 UVM Scoreboards and Environments 4 Topics

1. Scoreboards and Environments
2. Knowledge Check 1: UVM Scoreboards and Environments
3. Lab: UVM Scoreboards
4. Assessment: UVM Scoreboards

7 UVM Configuration and Factory 7 Topics

1. Configuration Introduction
2. Configuration HDL to Test Example
3. Knowledge Check 1: UVM Configuration
4. Factory Introduction
5. Knowledge Check 2: UVM Configuration and Factory
6. Lab: UVM Configuration and Factory
7. Assessment: UVM Configuration and Factory

8 UVM Tests and Virtual Sequences 4 Topics

1. UVM Test Class and Virtual Sequences
2. Knowledge Check 1: UVM Tests and Virtual Sequences
3. Lab: UVM Tests and Virtual Sequences
4. Assessment: UVM Tests and Virtual Sequences

9 Complex Sequences 3 Topics

1. Complex Sequences
2. Knowledge Check 1: Complex Sequences
3. Assessment: Complex Sequences

10 UVM Register Layer Introduction 1 Topic

1. UVM Register Layer Introduction

ReqTracer FPGA/ASIC Design Assurance Recordings 4  Chapters

Learn how to use ReqTracer to automate tracing of design requirements to design and test data associated with an FPGA/ASIC design by watching live recordings.

1 Requirements Tracing Concepts and Project Setup 3 Topics

1. Requirements Tracing Concepts and Project Setup
2. Lab 1: Project Setup
3. Assessment

2 Coverage Links, Tagging and Connecting to Verification Results 5 Topics

1. Coverage LINKS and TAGGING
2. Lab 2: Tracing and Tagging
3. Connecting to Verification Results
4. Lab 3: Verification Lab
5. Assessment

3 Reporting 3 Topics

1. Reporting
2. Lab 4: Reporting
3. Assessment

4 Using ReqTracer in a Team Environment 5 Topics

1. Using ReqTracer in a Team Environment
2. Demo: Using ReqTracer in a Team Environment
3. Additional Topics
4. Wrap-up
5. Assessment

SystemVerilog for Verification Exam 1  Chapter

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SystemVerilog UVM Exam 1  Chapter

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UVM Intermediate Exam 1  Chapter

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Questa Core HDL Simulation Exam 1  Chapter

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UVM Framework Exam 1  Chapter

Earners of this badge have successfully completed the 25 question exam to show basic knowledge of UVM Framework and how to use it to create a UVM testbench.

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Earners of this badge have successfully completed the 50 question exam to show mastery of using Questa’s advanced functional verification environment to manage

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ModelSim/Questa Core: Advanced Topics Exam 1  Chapter

Earners of this badge have successfully completed the 50-question exam to show advanced knowledge of how to use the Questa platform or ModelSim software.

1 ModelSim/Questa Core: Advanced Topics Exam 1 Topic

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Visualizer Debug Environment Exam 1  Chapter

Demonstrate your skills and knowledge in using Visualizer Debug Environment to navigate and debug design HDL and testbench code.

1 Visualizer Debug Environment Exam - v22.18.01 1 Topic

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HDL Designer Series Exam 1  Chapter

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Questa Power Aware and UPF Exam 1  Chapter

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1 Questa Power Aware and UPF Exam 1 Topic

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